MPC852TVR100 Freescale Semiconductor, MPC852TVR100 Datasheet - Page 12

• Manufacturer Part Number: MPC852TVR100
• Description: IC MPU POWERQUICC 100MHZ 256PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC852TVR100

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 100MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Layout Practices
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the
mandatory value in
11 Layout Practices
Each V
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The V
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip V
minimum, a four-layer board employing two inner layers as V
All output pins on the MPC852T have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized to minimize undershoot and reflections that these fast output switching times cause. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the
PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads, because these loads create higher transient currents in the V
inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL
12
DD
pin on the MPC852T should be provided with a low-impedance path to the board’s supply. Each GND
HRCW
(Hardware reset configuration word)
SIUMCR
(SIU module configuration register)
MBMR
(Machine B mode register)
PAPAR
(Port A pin assignment register)
PADIR
(Port A Data Direction Register)
PBPAR
(Port B Pin Assignment Register)
PBDIR
(Port B Data Direction Register)
PCPAR
(Port C Pin Assignment Register)
PCDIR
(Port C Data Direction Register)
Table 6
Register/Configuration
DD
power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors
in the boot code after the reset deasserts.
Table 6. Mandatory Reset Configuration of MPC852T
DD
MPC852T Hardware Specifications, Rev. 3.1
and GND should be kept to less than half an inch per capacitor lead. At a
HRCW[DBGC]
SIUMCR[DBGC]
MBMR[GPLB4DIS}
PAPAR[4-7]
PAPAR[12-15]
PADIR[4-7]
PADIR[12-15]
PBPAR[14]
PBPAR[16-23]
PBPAR[26-27]
PBDIR[14]
PBDIR[16-23]
PBDIR[26-27]
PCPAR[8-11]
PCDIR[14]
PCDIR[8-11]
PCDIR[14]
DD
Field
and GND planes should be used.
DD
and GND circuits. Pull up all unused
(binary)
Value
Freescale Semiconductor
X1
X1
0
0
1
0
1
0
1