UDA1345TS/N2,118 NXP Semiconductors, UDA1345TS/N2,118 Datasheet - Page 21

• Manufacturer Part Number: UDA1345TS/N2,118
• Description: IC AUDIO CODED 24BIT 28SSOP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1345TS/N2,118

• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 94 / 98
• Voltage - Supply, Analog: 2.4 V ~ 3.6 V
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 100 KSPS
• Interface Type: Serial (I2S) or L3
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/ 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935266777118; UDA1345TSDB-T; UDA1345TSDB-T

NXP Semiconductors
12 AC CHARACTERISTICS (DIGITAL)
V
(pins 1, 11, 22 and 27); unless otherwise specified.
2002 May 28
System clock timing; see Fig.7
T
t
t
t
t
Serial input/output data timing; see Fig.8
t
t
t
t
t
t
t
t
)
t
t
t
t
Address and data transfer mode timing; see Figs 4 and 5
T
t
t
t
t
t
t
DDD
CWL
CWH
r
f
BCK
BCKH
BCKL
r
f
s(DATAI)
h(DATAI)
d(DATAO−BCK
d(DATAO−WS)
h(DATAO)
s(WS)
h(WS)
HC
LC
s(MA)
h(MA)
s(MT)
h(MT)
SYMBOL
sys
cy
Economy audio CODEC
= V
DDA
= V
system clock cycle
f
f
rise time
fall time
bit clock period
bit clock HIGH time
bit clock LOW time
rise time
fall time
data input set-up time
data input hold time
data output delay time (from BCK
falling edge)
data output delay time (from WS edge) MSB-justified format
data output hold time
word select set-up time
word select hold time
L3CLOCK cycle time
L3CLOCK HIGH period
L3CLOCK LOW period
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
sys
sys
DDO
LOW-level pulse width
HIGH-level pulse width
= 2.7 to 3.6 V; T
PARAMETER
amb
= −20 to +85 °C; R
f
f
f
f
f
f
f
address mode
address mode
data transfer mode
data transfer mode
sys
sys
sys
sys
sys
sys
sys
21
= 256f
= 384f
= 512f
< 19.2 MHz
≥ 19.2 MHz
< 19.2 MHz
≥ 19.2 MHz
CONDITIONS
L
= 5 kΩ; all voltages referenced to ground
s
s
s
; note 1
; note 1
; note 2
39
26
36
0.30T
0.40T
0.30T
0.40T
−
−
1
34
34
−
−
20
0
−
−
0
20
10
500
250
250
190
190
190
190
⁄
128
MIN.
f
s
sys
sys
sys
sys
88
59
44
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TYP.
UDA1345TS
Product specification
488
325
244
0.70T
0.60T
0.70T
0.60T
20
20
−
−
−
20
20
−
−
80
80
−
−
−
−
−
−
−
−
−
−
MAX.
sys
sys
sys
sys
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT