CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 50

• Manufacturer Part Number: CS42325-CQZ
• Description: IC CODEC STEREO AUDIO 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

50
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.6
6.6.1
SP2_M/S
Reserved
7
7
Serial Port 2 Control (Address 04h)
ADC Clocking (Address 06h)
Serial Port 2 Master/Slave Select
This bit configures Serial Port 2 to operate as either a clock master or clock slave.
Serial Port 2 Speed Mode
In Master Mode this bit configures the speed mode of Serial Port 2.
MCLK2 Divider
These bits configure the internal MCLK2 dividers.
Serial Port 2 MCLK Source
This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 2.
ADC MCLK Source
This bit selects which MCLK pin provides the clock for the ADC.
0
1
0
1
00
01
10
11
0
1
0
1
SP2_SPEED
ADC_MCLK
SP2_MCLK
FREQ[1:0]
SP2_M/S
MCLK2
ADC_MCLK
Reserved
6
6
Slave Mode
Master Mode
Single-Speed Mode (SSM)
Double-Speed Mode (DSM)
÷1
÷1.5
÷2
÷3
MCLK1
MCLK2
MCLK1
MCLK2
Reserved0
Reserved
5
5
SP2_SPEED
ADC_SP
4
4
Serial Port 2 Master/Slave Select
Serial Port 2 MCLK source
Serial Port 2 Speed Mode
Reserved
MCLK2
FREQ1
ADC MCLK source
MCLK Divider
3
3
Reserved
MCLK2
FREQ0
2
2
ADC_DIF1
Reserved
1
1
CS42325
SP2_MCLK
ADC_DIF0
DS838A2
0
0