CS42325-CQZ Cirrus Logic Inc, CS42325-CQZ Datasheet - Page 52

• Manufacturer Part Number: CS42325-CQZ
• Description: IC CODEC STEREO AUDIO 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42325-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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6.8
6.8.1
6.8.2
6.8.3
6.9
6.9.1
6.9.2
Reserved
Reserved
7
7
DAC2 Clocking (Address 08h)
ADC Control (Address 0Ah)
DAC2 MCLK Source
This bit selects which MCLK pin provides the clock for DAC2.
DAC2 Serial Port Source
This bit selects which serial port provides the sub clocks for the DAC2.
DAC2 Digital Interface Format (DAC2_DIF)
These bits configure the serial audio interface format for incoming digital audio data on SDIN2.
ADC High-Pass Filter Freeze
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADC_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC mea-
surements, this bit must be set to ‘1’.
ADC Soft Ramp Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
00
01
10
11
0
1
0
1
0
1
DAC2_MCLK
ADC_HPFRZ
DAC2_DIF[1:0]
DAC2_SP
DAC2_MCLK
ADC_HPFRZ
6
6
Continuous DC Subtraction
Fixed DC Subtraction
MCLK1
MCLK2
Serial Port 1 (SCLK1/LRCK1)
Serial Port 2 (SCLK2/LRCK2)
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
ADC_SOFT
Reserved
5
5
DAC2_SP
Reserved
4
4
DAC2 Serial Audio Interface Format
ADC High-Pass Filter Freeze
DAC2 sub clock source
Reserved
Reserved
DAC2 MCLK source
3
3
AIN_SEL2
Reserved
2
2
DAC2_DIF1
AIN_SEL1
1
1
CS42325
DAC2_DIF0
AIN_SEL0
DS838A2
0
0