ADAU1328BSTZ Analog Devices Inc, ADAU1328BSTZ Datasheet - Page 14

• Manufacturer Part Number: ADAU1328BSTZ
• Description: IC CODEC 24BIT 2ADC/8DAC 48LQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of ADAU1328BSTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 94 / 94
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 106
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 108dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1328
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited
to less than 300 ps rms time interval error (TIE). Even at these
levels, extra noise or tones can appear in the DAC outputs if the
jitter spectrum contains large spectral peaks. If the internal PLL
is not being used, it is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
especially important that the clock signal not be passed through
an FPGA, CPLD, or other large digital chip (such as a DSP)
before being applied to the ADAU1328. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
Reset sets all the control registers to their default settings. To
avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires lock condition,
an initialization routine runs inside the ADAU1328. This
initialization lasts for approximately 256 MCLKs.
Table 10. Standalone Mode Selection
ADC Clocks
Slave
Master
CLATCH
COUT
CCLK
CIN
t
COE
t
CLS
D23
CIN/ADR0
0
0
t
CCP
D22
t
COD
D9
D9
t
CCH
COUT/SDA
0
1
Figure 11. Format of SPI Signal
t
t
CDS
CCL
D8
D8
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t
CDH
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained.
The reset pin should be pulled low by an external resistor to
guarantee proper startup.
SERIAL CONTROL PORT
The ADAU1328 has an SPI control port that permits
programming and reading back of the internal control registers
for the ADCs, DACs, and clock system. There is also a stand-
alone mode available for operation without serial control that is
configured at reset using the serial control pins. All registers are
set to default, except the internal MCLK enable is set to 1 and
ADC BCLK and LRCLK master/slave is set by COUT/SDA.
Refer to Table 10 for details. It is recommended to use a weak
pull-up resistor on CLATCH in applications that have a
microcontroller. This pull-up resistor ensures that the
ADAU1328 recognizes the presence of a microcontroller.
The SPI control port of the ADAU1328 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
ADAU1328, the address is 0x04, shifted left 1 bit due to the
R/ W bit. The second byte is the ADAU1328 register address
and the third byte is the data.
CCLK/SCL
0
0
t
CLH
CLATCH/ADR1
0
0
D0
D0
t
COTS