IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 16

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
2.2.
2.2.1.
2.2.2.
AC Timing Characteristics
RESET# active low pulse width
RESET# inactive to SDATA_IN or BIT_CLK active delay
RESET# inactive to BIT_CLK startup delay
BIT_CLK active to RESET# asserted (Not shown in diagram)
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
SDATA_IN
BIT_CLK
BIT_CLK
RESET#
SYNC
(T
load for BIT_CLK and 60pF external load for SDATA_IN)
Cold Reset
Warm Reset
Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.
ambient
= 25 °C, AVdd = 3.3V or 5V ± 5%, DVdd = 3.3V ± 5%, AVss = DVss = 0V; 75pF external
Parameter
Parameter
Figure 3. Warm Reset Timing
Figure 2. Cold Reset Timing
Tsync_high
16
Tres_low
Tsync_high
Tsync2clk
Tres_low
Symbol
Tri2actv
Trst2clk
Tclk2rst
Symbol
Tsync_2clk
Ttri2actv
Ttri2actv
Trst2clk
STAC9752A/9753A
.01628
0.416
162.8
Min
Min
1.0
1.0
-
Typ
Typ
1.3
-
-
-
-
-
Max
Max
400
25
-
-
-
-
PC AUDIO
V 1.5 1206
Units
Units
ns
ns
s
s
s
s