IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 64

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
7.1.20.
VCFG
D15
D7
one of three secondary CODECs. The AMAP bit, D9, will return a 1 indicating that the CODEC sup-
ports the optional “AC’97 2.3 Compliant AC-Link Slot to Audio DAC Mappings”. The default condition
assumes that 00 is loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 00
in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification recom-
mendations. If the DSA1 and DSA0 bits do not contain 00, the slot assignments are as per the table
in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicat-
ing that the CODEC supports the optional variable sample rate conversion as defined by the AC’97
specification.
Extended Audio Control/Status (2Ah)
Default: 0400h* (*default depends on CODEC ID)
15:14
13:12
11:10
9:6
5:4
Note: 1) External CID pin status (from analog), these bits are the logical inversion of the pin polarity (pin
Note: 2) If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available.
Bit
3
2
1
0
Reserved
45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source (in
primary mode only). Secondary mode can either be through BIT CLK driven or 24MHz clock driver,
with XTAL_OUT floating.
To disable SPDIF, use an 1K - 1 0 K external pullup resistor.
Reserved
DSA [1,0]
REV[1:0]
ID [1,0]
SPDIF
RSVD
RSVD
RSVD
Name
VRA
D14
D6
Read/Write
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Access
SPSA1
D13
D5
Table 19. Extended Audio ID Register Functions
Reserved
Reset Value
variable
00
10
00
0
0
1
0
1
SPSA0
D12
64
D4
00 = XTAL_OUT grounded (Note Note:)
CID1#,CID0# = XTAL_OUT crystal or floating
Bits not used, should read back 00
Indicates CODEC is AC’97 Rev 2.3 compliant
Reserved
DAC slot assignment
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
If CID[1:0] = 11 then DSA[1:0] resets to 10
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
Reserved
0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note Note:)
Reserved
Variable sample rates supported (Always = 1)
RSRVD
D11
D3
STAC9752A/9753A
SPDIF
SPCV
D10
D2
Function
RSRVD
D9
D1
Reserved
PC AUDIO
VRA enable
V 1.5 1206
D8
D0