IDTSTAC9758XXTAEB1XR IDT, Integrated Device Technology Inc, IDTSTAC9758XXTAEB1XR Datasheet - Page 39

• Manufacturer Part Number: IDTSTAC9758XXTAEB1XR
• Description: IC CODEC AC'97 6CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9758XXTAEB1XR

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9758XXTAEB1XR

IDT™
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
1. There are several subsections within an AC‘97 CODEC that can independently go busy/ready. It is the responsibility of the
AC’97 Controller to probe more deeply into the AC‘97 CODEC’s register file to determine which subsections are actually ready.
(See section 8.5. for Extended CODEC Registers Page Structure Definition, on page 85 for more information.)
5.4.1.
Slot 0: TAG
Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97
CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that
the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deasser-
tion of power-on-reset for example, while the AC‘97 CODEC’s voltage references settle. When the
AC-Link “CODEC Ready” indicator bit is a 1, it indicates that the AC-Link and AC‘97 CODEC control
and status registers are in a fully operational state. CODEC must assert “CODEC Ready” within
400 s after it starts receiving valid SYNC pulses from the controller, to provide an indication of con-
nection to the link and that Control/Status registers are available for access. The AC`97 Controller
and related software must wait until all of the lower four bits of the Control/Status Register, 26h, are
set before attempting any register writes, or attempting to enable any audio stream, to avoid undesir-
able audio artifacts.
Prior to any attempts at putting an AC‘97 CODEC into operation the AC‘97 Controller should poll the
first bit in the AC-Link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone
“CODEC Ready”. Once an AC‘97 CODEC is sampled “CODEC Ready”
tions sampled by the AC‘97 Controller indicate which of the corresponding 12 time slots are
assigned to input data streams, and that they contain valid data.
5.4.1.1.
18-12
1, 0
Bit
19
11
10
Slot 1: Status Address Port / SLOTREQ Signaling Bits
7
6
5
4
3
9
8
2
RESERVED (Set to 0)
Control Register Index Echo (Set to all 0 if tagged “invalid” by AC‘97 CODEC.)
On Demand Data Request Flags for slots 11-2 (next output frame):
0 = send data
1 = do NOT send data
RESERVED (Set to 0)
Note: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 3 request: PCM Left channel
Slot 5 request: RESERVED
Slot 6 request: PCM Center
Slot 7 request: PCM Left Surround
Slot 8 request: PCM Right Surround
Slot 9 request: PCM LFE
Slot 4 request: PCM Right channel
Slot 10 request: SPDIF
Slot 11 request: SPDIF
Slot 12 request: Interrupt Status and GPIO
Table 9. Input Slot 1 Bit Definitions
39
Description
STAC9758/9759
1
then the next 12 bit posi-
PC AUDIO
V 1.2 1206