UDA1342TS/N1,512 NXP Semiconductors, UDA1342TS/N1,512 Datasheet - Page 12

• Manufacturer Part Number: UDA1342TS/N1,512
• Description: IC AUDIO CODEC MINIDISC 28-SSOP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1342TS/N1,512

• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 99 / 99
• Voltage - Supply, Analog: 2.7 V ~ 3.6 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 2
• Conversion Rate: 110 KSPs
• Interface Type: Serial (I2C), L3
• Resolution: 24 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 4 ADC, 2 DAC
• Supply Current: 20 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1155-5; 935262909512; UDA1342TSDB

NXP Semiconductors
8.11
The UDA1342TS operates with sample frequencies from
16 to 110 kHz. This range holds for the CODEC as a
whole. The DAC part can be configured in the L3-bus and
I
speed (e.g. f
of the features can be used.
Some examples of the input oversampling rate settings are
shown in Table 4.
Table 4
8.12
The UDA1342TS has an internal Power-on reset circuit
(see Fig.7) which resets the test control block. All the
digital sound processing features and the system
controlling features are set to their default setting in the
L3-bus and I
The reset time (see Fig.8) is determined by an external
capacitor which is connected between pin V
The reset time should be at least 1 μs for V
When V
again for V
During the reset time the system clock should be running.
2000 Jul 31
2
12.288 MHz (256 × 48 kHz)
22.5792 MHz (512 × 44.1 kHz)
33.8688 MHz (768 × 44.1 kHz)
C-bus mode to accept 2 times and even 4 times the data
Audio CODEC
Sampling speed
Power-on reset
SYSTEM CLOCK
DDA(DAC)
Examples of the input oversampling rate settings
ref
s
2
C-bus mode.
< 0.75 V.
is 96 or 192 kHz), but in these modes not all
is switched off, the device will be reset
FREQUENCY
SETTING
SYSTEM
CLOCK
256f
512f
256f
768f
384f
ref
ref
s
s
s
s
s
and ground.
< 1.25 V.
FREQUENCY
SAMPLING
176.4
176.4
(kHz)
44.1
88.2
44.1
88.2
192
48
96
12
Important: in the double speed mode an input signal of
0 dB is allowed, but in the quad speed mode the input
signal must be limited to −6 dB to prevent the system from
clipping.
handbook, halfpage
single speed
double speed
quad speed
single speed
single speed
double speed
single speed
single speed
double speed
INPUT OVER-
SAMPLING
3.0 V
RATE
V DDA(DAC)
Fig.7 Power-on reset circuit.
C1 >
10 μF
V ref
25
28
only master volume and mute
no features
all
all
only master volume and mute
all
all
only master volume and mute
all
FEATURES SUPPORTED
8 kΩ
8 kΩ
UDA1342TS
UDA1342TS
CIRCUIT
Product specification
RESET
MGU001