AD1888JCP-REEL Analog Devices Inc, AD1888JCP-REEL Datasheet - Page 21

• Manufacturer Part Number: AD1888JCP-REEL
• Description: IC CODEC AUDIO-PC AC'97 48LFCSP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1888JCP-REEL

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 80 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 29. Extended Audio Status and Control Register (Index 2Ah)
Reg
No.
2Ah
The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers not shown and bits
containing an X are assumed to be reserved.
EVRA
EDRA
ESPDIF
SPSA[1,0]
ECDAC
ESDAC
ELDAC
SPCV
PRI
PRJ
PRK
VFORCE
Name
Extended
Audio
Stat/Ctrl
Variable Rate Audio (Read/Write).
EVRA = 0, sets fixed sample rate audio at 48 kHz (Reset Default).
EVRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).
Double Rate Audio.
EDRA = 1 enables double rate audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used in conjunction
with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the PCM front sample
rate control register. When using the double rate audio, only the front DACs are supported and all other DACs (surround, center,
and LFE) are automatically powered down. Note that EDRA can be used without VRA; in that case, the converter rates are forced
to 96 kHz if EDRA = 1.
SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).
ESPDIF = 1 enables the SPDIF transmitter.
ESPDIF = 0 disables the SPDIF transmitter (default).
SPDIF Slot Assignment Bits (Read/Write).
These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration. See the
following table.
Center DAC Status (Read Only).
ECDAC = 1 indicates the PCM center DAC is ready.
Surround DAC status (Read Only).
ESDAC = 1 indicates the PCM surround DACs are ready.
LFE DAC status (Read Only).
ELDAC = 1 indicates the PCM LFE DAC is ready.
SPDIF Configuration Valid (Read Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to
determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF
enable bit status.
SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported).
Center DAC Power-Down (Read/Write).
PRI = 1 turns off the PCM Center DAC.
Surround DACs Power-Down (Read/Write).
PRJ = 1 turns off the PCM surround DACs.
LFE DAC Power-Down (Read/Write).
PRK = 1 turns off the PCM LFE DAC.
Validity Force Bit (Reset Default = 0).
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be con-trolled by the V
bit (D15) in Register 3Ah (SPDIF control register).
VFORCE = 0 and V = 0; the Validity Bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and V = 0; the Validity Bit is forced low, indicating subframe data is valid.
VFORCE = 1 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid.
D15
VFORCE
D14
X
D13
PRK
D12
PRJ
D11
PRI
D10
SPCV
Rev. A | Page 21 of 32
D9
X
D8
ELDAC
D7
ESDAC
D6
ECDAC
D5
SPSA1
D4
SPSA0
D3
X
D2
ESPDIF
D1
EDRA
AD1888
D0
EVRA
Default
0xx0h