AD1888JSTZ Analog Devices Inc, AD1888JSTZ Datasheet - Page 12

• Manufacturer Part Number: AD1888JSTZ
• Description: IC CODEC AUDIO-PC AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1888JSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 80 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.15/4.75V
• Single Supply Voltage (max): 3.45/5.25V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1888
Table 7. Reset Register (Index 00h)
Reg No.
00h
All registers not shown and bits containing an X are assumed to be reserved.
Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1888 based on the following:
Bit = 1
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
SE[4:0] Stereo Enhancement. The AD1888 does not provide hardware 3D stereo enhancement. (All bits are zeros.)
Table 8. Master Volume Register (Index 02h)
Reg
No.
02h
1
2
Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality:
RMV[5:0]
MMRM
LMV[5:0]
MM
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set
to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.
Refer to Table 10 for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits,
For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If
MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved.
For AC97NC = 0, the register controls the Line_out output Attenuators only.
For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators.
Name
Master
Volume
Name
Reset
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a
maximum attenuation of 46.5 dB.
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MM
bit. Otherwise this bit will always read 0 and will have no effect when set to 1.
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
Headphones Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in
Register 76h is set to 1.
D15
MM
D15
X
Function
Dedicated Mic PCM In Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
D14
X
D14
SE4
D13
LMV5
1
D13
SE3
D12
LMV4
D12
SE2
D11
LMV3
D11
SE1
D10
LMV2
D10
SE0
D9
LMV1
Rev. A | Page 12 of 32
D9
ID9
D8
LMV0
D8
ID8
D7
MMRM
D7
ID7
2
D6
X
D6
ID6
D5
RMV5
1
D5
ID5
D4
RMV4
D4
ID4
D3
RMV3
D3
ID3
D2
RMV2
D2
ID2
AD1888
0
0
0
0
1
0
0
1
0
0
D1
ID1
D1
RMV1
ID0
D0
D0
RMV0
Default
0090h
Default
8000h