AD1888JSTZ Analog Devices Inc, AD1888JSTZ Datasheet - Page 16

• Manufacturer Part Number: AD1888JSTZ
• Description: IC CODEC AUDIO-PC AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1888JSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 80 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.15/4.75V
• Single Supply Voltage (max): 3.45/5.25V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1888
Table 19. PCM-Out Volume Register (Index 18h)
Reg
No.
18h
1
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 20 for examples.
Note that depending on the state of the AC97NC bit in Register 76h, this register has the following additional functionality:
ROV[4:0]
OMRM
LOV[4:0]
OM
Table 20. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Reg. 76h
MSPLT
0
0
0
0
1
1
1
1
If MSPLT is not set, RM Bit has no effect.
x in the above table is don’t care.
Table 21. Record Select Control Register (Index 1Ah)
Reg
No.
1Ah
All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table 22 for examples. Used to select the record source independently for the right and left channels. For MIC recording, see MS bit (Register 20h) for
MIC1 and MIC2 input selection.
RS [2:0]
LS [2:0]
For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
For AC97NC = 0, the register also controls the Surround, Center, and LFE DAC Gain/Attenuators.
For AC97NC = 1, the register controls the PCM Out Volume only.
For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
Name
PCM
Out
Volume
1
T
Name
Record
Select
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the
gain range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM
bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the
range is +12 dB to −34.5 dB. The default value is 0 dB, mute enabled.
PCM Out Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register
76h is set to 1, in which case this mute bit will affect only the left channel.
D15
0
0
0
1
0
1
1
D15
OM
WRITE
0 0000
0 1000
1 1111
x xxxx
1 1111
x xxxx
x xxxx
D14
X
D15
X
Left Channel Volume D[12:8]
READBACK
0 0000
0 1000
1 1111
x xxxx
1 1111
x xxxx
x xxxx
D13
X
D14
X
D12
LOV4
D13
X
D11
LOV3
Right Record Select
Left Record Select
Function
12 dB Gain
0 dB Gain
−34.5 dB Gain
−∞ dB Gain, Muted
−34.5 dB Gain
−∞ dB Gain, Left Only Muted
−∞ dB Gain, Left Muted
D12
X
Line-In (10h), CD (12h), AUX (16h) and PCM-Out (18h)
D10
LOV2
D11
X
D9
LOV1
Rev. A | Page 16 of 32
D10
LS2
D8
LOV0
D9
LS1
Control Bits
D7
OMRM
D8
LS0
D7
x
x
x
x
1
0
1
1
1
D7
X
WRITE
0 0000
0 1000
1 1111
x xxxx
x xxxx
1 1111
x xxxx
D6
X
D6
X
D5
X
Right Channel Volume D[4:0]
READBACK
0 0000
0 1000
1 1111
x xxxx
x xxxx
1 1111
x xxxx
D5
X
D4
ROV4
D4
X
D3
ROV3
D3
X
Function
12 dB Gain
0 dB Gain
−34.5 dB Gain
−∞ dB Gain, Muted
−∞ dB Gain, Right Only Muted
−34.5 dB Gain
−∞ dB Gain, Right Muted
D2
ROV2
RS2
D2
D1
RS1
D1
ROV1
D0
RS0
D0
ROV0
Default
0000h
Default
8808h