AD1888JSTZ Analog Devices Inc, AD1888JSTZ Datasheet - Page 18

• Manufacturer Part Number: AD1888JSTZ
• Description: IC CODEC AUDIO-PC AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1888JSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 80 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.15/4.75V
• Single Supply Voltage (max): 3.45/5.25V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1888
Table 25. General-Purpose Register (Index 20h)
Reg
No.
20h
This register should be read before writing to generate a mask only for the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed
to be reserved.
LPBK
MS
DRSS [1:0]
Table 26. Audio Interrupt and Paging Mechanism Register (Index 24h)
Reg
No.
24h
This register controls the audio interrupt and paging mechanism. All registers not shown and bits containing an X are assumed to be reserved.
PG[3:0]
I0
I4
Name
Audio
Interrupt and
Paging
Name
General-
Purpose
Page Selector (Read Only). This register is used to describe page selector capability for extended features. Reading these bits
returns 0h, which describes page selection as vendor specific only.
INTERRUPT ENABLE (R/W). This enables interrupt generation.
0 = Interrupt Generation is Masked (Default)
1 = Interrupt Generation is Unmasked
The S/W should not unmask the interrupt unless ensured by the AC ’97 controller that no conflict is possible with modem slot 12
GPI functionality.
AC ’97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, S/W could poll the
interrupt status after initiating a sense cycle and waiting for Sense Cycle Max Delay to determine if an interrupting event has
occurred.
INTERRUPT STATUS (R/W). This bit provides interrupt status and clear capability.
0 = Interrupt is Clear
1 = Interrupt was Generated
Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0)
status. An interrupt in the GPI in slot 12 in the ac link will follow this bit change when interrupt enable (I0) is unmasked.
Loopback Control. This bit enables the digital internal loopback from the ADC to the front DAC. This feature is normally used
for test and troubleshooting.
0 = No Loopback (Default)
1 = Loopback PCM digital data from ADC output to DAC
See LBKS bit in Register 0x74 for changing the loopback path to use the Surround or Center/LFE DACs.
MIC Select. Selects Mono MIC input.
0 = Select MIC1, from rear panel MIC jack
1 = Select MIC2, from front panel MIC jack
Double Rate Slot Select. The DRSS bits specify the slots for the n + 1 sample outputs. PCM L (n + 1) and PCM R (n + 1) data are
by default provided in output slots 10 and 11.
00: PCM L, R n + 1 Data is on Slots 10, 11 (reset default)
01: PCM L, R n + 1 Data is on Slots 7, 8
10: Reserved
11: Reserved
D15
X
D15
I4
D14
X
D14
X
D13
X
D13
X
D12
X
D12
X
D11
DRSS1
D11
I0
D10
DRSS0
D10
X
Rev. A | Page 18 of 32
D9
X
D9
X
D8
X
D8
MS
D7
X
D7
LPBK
D6
X
D6
X
D5
X
D5
X
X
D4
D4
X
D3
PG3
D3
X
D2
PG2
D2
X
D1
PG1
D1
X
D0
PG0
D0
X
Default
0000h
Default
xxxxh