KSZ8873RLL Micrel Inc, KSZ8873RLL Datasheet - Page 28

• Manufacturer Part Number: KSZ8873RLL
• Description: IC ETHERNET SWITCH 3PORT 64-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873RLL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: RMII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Ports: 3
• Ethernet Type: IEEE 802.3u
• Supply Current: 115mA
• Supply Voltage Range: 2.5V, 3.3V
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (15-Dec-2010)
• Base: RoHS Compliant
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Interface Type: MII, RMII
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3461

Micrel, Inc.
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:
1. Aggressive back-off (register 3 (0x03), bit [0])
2. No excessive collision drop (register 4 (0x04), bit [3])
Note: These bits are not set as defaults, as this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8873MLL/FLL/RLL has an intelligent option to protect the switch system from receiving too many broadcast
packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch
resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8873MLL/FLL/RLL has the option
to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can
be enabled or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT.
At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number
of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting is 0x63
(99 decimal). This is equal to a rate of 1%, calculated as follows:
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes of
preamble between two packets.
Port Individual MAC address and Source Port Filtering
The KSZ8873MLL/FLL/RLL provide individual MAC address for port 1 and port 2 respectively. They can be set at register
142-147 and 148-153. With this feature, the CPU connected to the port 3 can receive the packets from two internet
subnets which has their own MAC address.
The packet will be filtered if its source address matches the MAC address of port 1 or port 2 when the register 21 and 37
bit 6 is set to 1 respectively. For example, the packet will be dropped after it completes the loop of a ring network.
MII Interface Operation
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by the KSZ8873MLL/FLL is connected to the
device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception.
The following table describes the signals used by the MII bus.
September 2009
PHY-Mode Connections
External MAC
Controller Signals
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63
KSZ8873MLL/FLL
PHY Signals
SMTXEN3
SMTXER3
SMTXD33
SMTXD32
SMTXD31
SMTXD30
SMTXC3
SCOL3
SCRS3
SMRXDV3
(not used)
SMRXD33
SMRXD32
SMRXD31
SMRXD30
SMRXC3
Pin
Descriptions
Transmit enable
Transmit error
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Transmit clock
Collision detection
Carrier sense
Receive data valid
Receive error
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
Receive clock
Table 4. MII Signals
28
MAC-Mode Connections
External
PHY Signals
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
KSZ8873MLL/FLL
MAC Signals
SMRXDV3
(not used)
SMRXD33
SMRXD32
SMRXD31
SMRXD30
SMRXC3
SCOL3
SCRS3
SMTXEN3
SMTXER3
SMTXD33
SMTXD32
SMTXD31
SMTXD30
SMTXC3
KSZ8873MLL/FLL/RLL
M9999-092309-1.2