KSZ8873RLL Micrel Inc, KSZ8873RLL Datasheet - Page 42

• Manufacturer Part Number: KSZ8873RLL
• Description: IC ETHERNET SWITCH 3PORT 64-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873RLL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: RMII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Ports: 3
• Ethernet Type: IEEE 802.3u
• Supply Current: 115mA
• Supply Voltage Range: 2.5V, 3.3V
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (15-Dec-2010)
• Base: RoHS Compliant
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Interface Type: MII, RMII
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3461

Micrel, Inc.
Loopback Support
The KSZ8873MLL/FLL/RLL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at
both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end
(Remote) Loopback.
Far-end Loopback
Far-end loopback is conducted between the KSZ8873MLL/FLL/RLL’s two PHY ports. The loopback is limited to few
package a time for diagnosis purpose and can not support large traffic. The loopback path starts at the “Originating.” PHY
port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating”
PHY port’s transmit outputs (TXP/TXM).
Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 0, bit [14] can be used to enable far-end loopback.
The far-end loopback path is illustrated in the following figure.
September 2009
R X P /
R X M
Figure 14. Far-End Loopback Path
P M D /P M A
P M D /P M A
S w itc h
O rigina ting
P H Y P ort
L o op B ack
P H Y P o rt
M A C
M A C
P C S
P C S
42
T X P /
T X M
KSZ8873MLL/FLL/RLL
M9999-092309-1.2