MFRC52201HN1,157 NXP Semiconductors, MFRC52201HN1,157 Datasheet - Page 23

• Manufacturer Part Number: MFRC52201HN1,157
• Description: IC SMART CARD READER
• Manufacturer: NXP Semiconductors

Specifications of MFRC52201HN1,157

• Controller Type: Smart Card Interface
• Interface: SPI
• Voltage - Supply: 1.6 V ~ 3.6 V
• Current - Supply: 60mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280547157; MFRC52201HN1; MFRC52201HN1

NXP Semiconductors
112132
Product data sheet
9.2.1.14 BitFramingReg
9.2.1.15 CollReg
Adjustments for bit oriented frames.
Table 33:
Table 34:
Defines the first bit collision detected on the RF interface.
Table 35:
Table 36:
Bit
7
6 to 4
3
2 to 0
Bit
7
6
5
Symbol
Access
Symbol
Access
Rights
Rights
Bit
Bit
Symbol
ValuesAfterColl
-
CollPosNotValid
StartSend
AfterColl
Symbol
StartSend
RxAlign
-
TxLastBits
Description of BitFramingReg bits
CollReg register (address 0Eh); reset value: XXh
Description of CollReg bits
Values
BitFramingReg register (address 0Dh); reset value: 00h
r/w
7
w
7
RFU
Description
Set to logic 1, the transmission of data starts.
This bit is only valid in combination with the Transceive command.
Used for reception of bit oriented frames: RxAlign defines the bit position
for the first bit received to be stored in the FIFO. Further received bits are
stored at the following bit positions.
Example:
RxAlign = 0: the LSB of the received bit is stored at bit 0, the second
RxAlign = 1: the LSB of the received bit is stored at bit 1, the second
RxAlign = 7: the LSB of the received bit is stored at bit 7, the second
This bits shall only be used for bitwise anticollision at 106 kbit/s. In all
other modes it shall be set to 0.
Reserved for future use.
Used for transmission of bit oriented frames: TxLastBits defines the
number of bits of the last byte that shall be transmitted. A 000b indicates
that all bits of the last byte shall be transmitted.
Rev. 3.2 — 22 May 2007
6
-
6
Description
If this bit is set to logic 0, all receiving bits will be cleared after a
collision. This bit shall only be used during bitwise anticollision at
106 kbit/s, otherwise it shall be set to logic 1.
Reserved for future use.
Set to logic 1, if no collision is detected or the position of the collision
is out of the range of bits CollPos.
NotValid
CollPos
RxAlign
r/w
5
r
5
received bit is stored at bit position 1.
received bit is stored at bit position 2.
received bit is stored in the following byte at bit position 0.
4
4
RFU
3
3
-
CollPos
2
r
2
Contactless Reader IC
MFRC522
TxLastBits
© NXP B.V. 2007. All rights reserved.
r/w
1
1
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0
0