Z16C3220FSG Zilog, Z16C3220FSG Datasheet - Page 114

• Manufacturer Part Number: Z16C3220FSG
• Description: IC 20MHZ CMOS IUSC 80-QFP
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3220FSG

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z
PS97USC0200
ILOG
No
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
Symbol
TdWRr(TRQ)
TsCS(DS)
ThCS(DS)
TsADD(DS)
ThADD(DS)
TsSIA(DS)
ThSIA(DS)
TsCS(RD)
ThCS(RD)
TsADD(RD)
ThADD(RD)
TsSIA(RD)
ThSIA(RD)
TsCS(WR)
ThCS(WR)
TsADD(WR)
ThADD(WR)
TsSIA(WR)
ThSIA(WR)
TdDSf(RDY)
TdRDY(DRv)
TdDSr(RDY)
TsIEI(DSI)
ThIEI(DSI)
TdIEI(IEO)
TdAS(IEO)
TdDSI(INT)
TdDSI(Wf)
TdDSI(Wr)
TdW(DRv)
TdRDf(RDY)
TdRDr(RDY)
TsIEI(RDI)
ThIEI(RDI)
TdRDI(INT)
TdRDI(Wf)
TdRDI(Wr)
TwPIAl
TwPIAh
TdAS(PIA)
TdPIA(AS)
TdPIA(DRa)
TdPIA(DRn)
TdPIA(DRz)
Parameter
/WR Rise to /TxREQ Active Delay
/CS to /DS Fall Setup Time
/CS to /DS Fall Hold Time
Direct Address to /DS Fall Setup Time
Direct Address to /DS Fall Hold Time
Status /INTACK to /DS Fall Setup time
Status /INTACK to /DS Fall Hold Time
/CS to /RD Fall Setup Time
/CS to /RD Fall Hold Time
Direct Address to /RD Fall Setup Time
Direct Address to /RD Fall Hold Time
Status /INTACK to /RD Fall Setup Time
Status /INTACK to /RD Fall Hold Time
/CS to /WR Fall Setup Time
/CS to /WR Fall Hold Time
Direct Address to /WR Fall Setup Time
Direct Address to /WR Fall Hold Time
Status /INTACK to /WR Fall Setup Time
Status /INTACK to /WR Fall Hold Time
/DS Fall (Intack) to /RDY Fall Delay
/RDY Fall to Data Valid Delay
/DS Rise to /RDY Rise Delay
IEI to /DS Fall (Intack) Setup Time
IEI to /DS Rise (Intack) Hold Time
IEI to IEO Delay
/AS Rise (Intack) to IEO Delay
/DS Fall to /INT Inactive Delay
/DS Fall (Intack) to /WAIT Fall Delay
/DS Fall (Intack) to /WAIT Rise Delay
/WAIT Rise to Data Valid Delay
/RD Fall (Intack) to /RDY Fall Delay
/RD Rise to /RDY Rise Delay
IEI to /RD Fall (Intack) Setup Time
IEI to /RD Rise (Intack) Hold Time
/RD Fall (Intack) to /INT Inactive Delay
/RD Fall (Intack) to /WAIT Fall Delay
/RD Fall (Intack) to /WAIT Rise Delay
Pulsed /INTACK Low Width
Pulsed /INTACK High Width
/AS Rise to Pulsed /INTACK Fall Delay Time
Pulsed /INTACK Rise to /AS Fall Delay Time
Pulsed /INTACK Fall to Data Active Delay
Pulsed /INTACK Rise to Data Not Valid Delay
Pulsed /INTACK Rise to Data Float Delay
P R E L I M I N A R Y
Min
25
25
25
25
25
25
25
25
25
60
60
70
60
0
0
0
0
0
5
5
5
5
0
5
5
0
0
5
5
Max
200
200
200
200
200
200
40
40
60
60
40
40
40
40
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Z16C32 IUSC
Note
[1,2]
[1,2]
[1,2]
[1,2]
[1,2]
[1,2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
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