Z16C3220FSG Zilog, Z16C3220FSG Datasheet - Page 14

• Manufacturer Part Number: Z16C3220FSG
• Description: IC 20MHZ CMOS IUSC 80-QFP
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3220FSG

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Another method by which the DMA and serial channel
work together is using the Transmit Character Counter to
break a large block of data into a number of fixed length
frames. For example, it is desired to transmit a large file
which is located in several memory buffers as fixed length
smaller frames. With the IUSC, the serial channel is pro-
grammed to send the end-of-frame sequence each time
the set number of bytes is transmitted. Therefore, DMA
transfers are not interrupted, nor is system response
required to break the large file into frames.
Z
PS97USC0200
ILOG
Figure 5. Linked List Mode with Linked Frame Status Transfer and Ring Buffer Features
Buffer 1 RSBR or 0
Buffer 1 RSHR or 0
Buffer 1 Address
Buffer 1 Length
Link Address
of Entry2
0
Ring Buffer Mode
Writes this word
to 0 after it is read.
Integrated Frame Status
Transfer writes the Receive
Status Block (or 0) here.
P R E L I M I N A R Y
Buffer 2 RSBR or 0
Buffer 2 RSHR or 0
Buffer 2 Address
Buffer 2 Length
Link Address
of Entry3
0
The IUSC provides higher throughput than discrete serial
and DMA chip solutions because discrete chips do not
directly communicate with each other and, therefore, the
status of one device must be read by the CPU and
communicated to the other. This typically requires inter-
rupts and the suspension of activity until status/control
information is updated. This uses precious time and bus
bandwidth, which can limit total throughput.
Buffer 3 RSBR or 0
Buffer 3 RSHR or 0
Buffer 3 Address
Buffer 3 Length
Link Address
of Entry1
0
Z16C32 IUSC
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