Z16C3220FSG Zilog, Z16C3220FSG Datasheet - Page 28
![IC 20MHZ CMOS IUSC 80-QFP](/photos/6/76/67663/269-80-qfp_sml.jpg)
Z16C3220FSG
Manufacturer Part Number
Z16C3220FSG
Description
IC 20MHZ CMOS IUSC 80-QFP
Manufacturer
Zilog
Series
IUSC™r
Specifications of Z16C3220FSG
Controller Type
USC Controller
Interface
DMA
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
7mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-BQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Z
PS97USC0200
ILOG
Note:
Bit 12 in DCR is used to control the byte ordering of addresses and counts stored in memory in the
Array and Linked Array Modes. The above figure shows the two cases for both bus bandwidths.
Little End Array
Little End Array
Big End Array
Big End Array
(16-Bit bus)
(16-Bit bus)
(8-Bit bus)
(8-Bit bus)
Address n+2
Address n+2
Address n+1
Address n+2
Address n+3
Address n+1
Address n+2
Address n+3
Address n
Address n
Address n
Address n
AD15
AD15
AD7
AD7
31
15
15
31
31
23
15
07
07
15
23
31
Figure 13. Array-Chained Bit Ordering
30
14
14
30
30
22
14
06
06
14
22
30
29
13
13
29
29
21
13
05
05
13
21
29
P R E L I M I N A R Y
28
12
12
28
28
20
12
04
04
12
20
28
27
11
11
27
27
19
11
03
03
11
19
27
26
10
10
26
26
18
10
02
02
10
18
26
25
09
09
25
25
17
09
01
01
09
17
25
AD0
AD0
24
08
08
24
24
16
08
00
00
08
16
24
23
07
07
23
22
06
06
22
21
05
05
21
20
04
04
20
19
03
03
19
18
02
02
18
17
01
01
17
AD0
AD0
16
00
00
16
Z16C32 IUSC
28
™
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