Z8023010VSC Zilog, Z8023010VSC Datasheet
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Z8023010VSC
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... Z80230/Z85230/L Enhanced Serial Communications Controller Product Specification PS005308-0609 ® Copyright ©2009 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners. PS005308-0609 ...
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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Date June 2009 May 2009 May 2009 Mar ...
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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Z85230/L Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ...
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Pin Descriptions The Enhanced Serial Communication Controller (ESCC) pins are divided into seven func- tional groups: 1. Address/Data 2. Bus Timing and Reset 3. Device Control 4. Interrupt 5. Serial Data (both channels) 6. Peripheral Control (both channels) 7. Clocks ...
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Data Bus Bus Timing and Reset Control Interrupt Data Bus Bus Timing and Reset Control Interrupt PS005308-0609 D7 TxDA D6 RxDA D5 TRxCA D4 RTxCA D3 SYNCA D2 W/REQA D1 DTR/REQA D0 RTSA RD CTSA WR DCDA Z85230/L A/B TxDB ...
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Figure 3 displays the Z85230/L DIP and PLCC pin assignments, respectively. displays the Z80230 DIP and PLCC pin assignments INT RD IEO WR IEI A/B INTACK CE VCC D/C W/REQA ...
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Pins Common to Both Z85230/L and Z80230 The pin descriptions for pins common to both Z85230/L and Z80230 are provided below: CTSA, CTSB (Clear To Send (Inputs, Active Low))— enables if they are programmed for AUTO ENABLE (WR3 bit 5 ...
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When used as DMA Request line (WR14 bit 2 is 1), the timing for the deactivation request can be programmed in Write Register 7 deactivated with the same timing as the W/REQ pin the deactivation timing of DTR/ ...
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INT (Interrupt (Output, Open-Drain, Active Low))— requests an interrupt. The INT is an open-drain output. INTACK (Interrupt Acknowledge (Input, Active Low))— cates that an Interrupt Acknowledge Cycle is in progress. During this cycle, the ESCC interrupt daisy chain is resolved. ...
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CS0 (Chip Select 0 (Input, Active Low))— addresses on A7-A0 and must be Low for the intended bus transaction to occur. CS1 (Chip Select 1 (Input, Active High))— before and during the intended bus transaction. DS (Data Strobe (Input, Active ...
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... The details of the communication between the receive and transmit logic of the system bus are displayed in Figure 5 the ESCC A and B channels are identical. For more information on SCC/ESCC and ISCC Family of Products, refer to the respective User Manuals available for download from www.zilog.com. WR7 SYNC Register 20-Bit TX Zero Insert ...
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Lower Byte (WR12) Upper Byte (WR13) Time Constant Time Constant 16 Bit Down Counter BRG Input DPLL IN DPLL Internal TXD MUX RxD 1 Bit Input/Output Capabilities System communication to and from the ESCC is accomplished using the ESCC ...
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Throughout this document the Write and Read registers are referenced with the notations Note: WR for Write Register and RR for Read Register. For example: WR4A – Write Register 4 for Channel A RR3 – Read Register 3 for either ...
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Table 2. ESCC Read Registers Register Name RR0 RR1 RR2A RR2B RR3A RR4 RR5 RR6 RR7 RR8 RR9 RR10 RR11 RR12 RR13 RR14 RR15 There are three modes used to move data into and out of the ESCC: 1. POLLING ...
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Pending register. Status information for both channels resides in one register. Only one register may be read. Depending on its contents, the CPU performs one of the three opera- tions listed below: 1. Write data 2. Read data 3. Continues ...
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CC IEI A7–A0INT INTACKIEO A7–A0 INT INTACK Figure 7. ESCC Interrupt Priority Schedule The ESCC can also execute an Interrupt Acknowledge cycle using software. Sometimes it is difficult to create the INTACK signal with the necessary timing to acknowledge ...
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When the receiver is enabled, the CPU is interrupted in one of the following three meth- ods: 1. Interrupt on First Receive Character or Special Receive Condition 2. Interrupt on All Receive Characters or Special Receive Conditions 3. Interrupt on ...
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CPU/DMA BLOCK TRANSFER The ESCC provides a BLOCK TRANSFER mode to accommodate CPU/DMA controller. The BLOCK TRANSFER mode uses the WAIT/REQUEST output in conjunction with the WAIT/REQUEST bits in WR1. The WAIT/REQUEST output can be defined as a WAIT line ...
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ASYNCHRONOUS Mode The ESCC has significant improvements over the standard Serial Communications Con- troller (SCC). The addition of the deeper data FIFOs provide greater protection against underruns and overruns as well as more efficient use of bus bandwidth. The deeper ...
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CRC checking for SYNCHRONOUS BYTE-ORIENTED mode is delayed by one charac- ter time so that the CPU may disable CRC checking on specific characters. This action permits the implementation of protocols such as IBM BISYNC. Both CRC-16 (X polynomials are ...
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NRZ, NRZI coding may be used in any 1X mode. The parity options available in ASYNCHRONOUS mode are also available in SYNCHRONOUS mode. However, parity checking is not normally used for SDLC because CRC checking is more robust. ...
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SDLC Status FIFO The ESCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10-bit deep by 19-bit wide status FIFO buffer. When enabled (through WR15 bit 2 is 1), the storage area enables DMA to continue ...
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For FM encoding, the DPLL counts from 0 to 32, but with a cycle corresponding to two bit times. When the DPLL is locked, the clock edges in the data stream occurs between counts 15 and 16 and between counts ...
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Table 3. Data Encoding Descriptions (Continued) Code Type FM1 (biphase mark) Additional Transition at the Center of the Bit Cell FM0 (biphase space) In addition to the four methods, ESCC can be used to decode Manchester (biphase level) data using ...
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Z80230/Z85230/L Enhancements A detailed description of the enhancements to the Z80230/Z85230/L ESCC that differenti- ate it from the standard SCC is provided below: 4-Byte Transmit FIFO Buffer The ESCC has a 4-byte transmit buffer with programmable interrupt and DMA request ...
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By resetting WR7’ bit applications which have a long latency to interrupts can gen- erate the request to read data from the FIFO when one byte is available. The application can then test the Receive Character Available ...
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... Bit 5 is set to 1 and all other bits are reset to 0 after a reset. For applications which use either the Zilog Z8X30SCC or Z80230, these two device types can be identified in software with the following test: 1 ...
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WR D7–D0 DTR/REQ WAIT/REQ Figure 12. DMA Request on Transmit Deactivation Timing Bit 3 (Receive FIFO Interrupt Level) This bit sets the interrupt level of the receive FIFO. If this bit is set to 1, the receive data available bit ...
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... Historically, the SCC latched the databus on the falling edge of WR. However, as many CPUs do not guarantee that the databus is valid when the WR pin goes Low, Zilog modi- fied the databus timing to allow a maximum delay from the WR signal going active Low to the latching of the databus. ...
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TBE interrupts even if a Reset Transmit Buffer Interrupt command for the data created interrupt is issued after the CRC interrupt occurs (Time the EOM latch resets before the end ...
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Software Interrupt Acknowledge The Z80230/Z85230/L interrupt acknowledge cycle can be initiated using software. If Write Register 9 (WR9 bit 5 is 1), Read Register 2 (RR2) results in an interrupt INTACK cycle, a software acknowledgment causes the INT pin to ...
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CPU verifies the previously received frame. SCC Status Register RR1 Residue Bits (3) Overrun, CRC Error 5 Bits 6-Bit MUX 2 Bits Interface to SCC See Notes:, next. Notes: 1. ...
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When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit counter and 5 status bits are loaded into the status FIFO for verification by the CPU. The CRC checker is automatically ...
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FIFO is empty). The read from RR1 allows an entry to be read from the FIFO (if the FIFO is empty, the logic prevents a FIFO underflow condition). FIFO Write Operation When the end of an SDLC ...
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Programming The ESCC contains write registers in each channel that are programmed by the system separately to configure the function of each channel. In the Z85230/L ESCC, the data FIFOs are directly accessible by selecting a High on the ...
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This bit is placed in this register to simplify programming when the current state of the Shift right/Shift Left bit is not known. A hardware reset forces SHIFT LEFT mode where the ...
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Table 5. Z80230 Register Map (Shift Left Mode) (Continued) AD5 AD4 AD3 ...
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Table 6 lists details of the Z80X30 Register Map in SHIFT RIGHT mode. Table 6. Z80X30 Register Map (Shift Right Mode) AD4 AD3 AD2 ...
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Bits 2–0 of WR0 select registers 0–7. With the Point High command, Registers 8–15 are selected. Table 7 Table 7. Z85230/L Register Map A/B PNT2 PNT1 ...
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Table 8 through Table 24 Table 8. Write Register 0 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit Position R/W Value 000 001 010 011 100 101 ...
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Table 9. Write Register 1 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 Description ...
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Table 10. Write Register 2 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 11. Write Register 3 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 12. Write Register 4 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 13. Write Register 5 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 Description ...
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Table 14. Write Register 6 Bit Reset R = Read W = Write X = Indeterminate Bit Monosync 8 Position R/W Value Bits 7 Sync7 6 Sync6 5 Sync5 4 Sync4 3 Sync3 2 Sync2 ...
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Table 15. Write Register 7 Bit Reset R = Read W = Write X = Indeterminate Bit R/W Value This Position column contains 7 no data PS005308-0609 5 ...
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Table 16. Write Register 7’ Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 17. Write Register 8 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 18. Write Register 9 Bit 7 R/W 1 Hardware Reset X Channel Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 19. Write Register 10 Bit 7 R/W 0 Hardware Reset 0 Channel Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 20. Write Register 11 Bit 7 R/W 0 Hardware Reset X Channel Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 21. Write Register 12 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 22. Write Register 13 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 23. Write Register 14 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 Description ...
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Table 24. Write Register 15 Bit 7 R/W 1 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position Read Registers The ESCC contains ten read registers (eleven, ...
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Table 25. Read Register 0 Bit R Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 26. Read Register 1 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 27. Read Register 2 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position These bits include status information when read from Channel ...
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Table 28. Read Register 3 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position Bits and 0 are ...
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Table 29. Read Register 4 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position This register reflects the contents of RR0 if WR7’ ...
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Table 30. Read Register 5 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position This register reflects the contents of RR1 if WR7’ ...
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Table 31. Read Register 6 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position This register can be accessed only if WR15 bit ...
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Table 32. Read Register 7 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position This register can be accessed only if WR15 bit ...
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Table 33. Read Register 8 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 34. Read Register 9 Bit 7 R/W 1 Hardware Reset X Channel Reset R = Read W = Write X = Indeterminate Bit R/W Value Position access this register WR7’ ...
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Table 35. Read Register 10 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 36. Read Register 11 Bit 7 R/W 0 Hardware Reset X Channel Reset R = Read W = Write X = Indeterminate Bit R/W Value Position access this register WR7’ ...
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Table 37. Read Register 12 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 38. Read Register 13 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Table 39. Read Register 14 Bit 7 R/W 0 Reset R = Read W = Write X = Indeterminate Bit R/W Value Position access this register WR7’ bit 6 must be ...
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Table 40. Read Register 15 Bit 7 R/W X Reset R = Read W = Write X = Indeterminate Bit R/W Value Position PS005308-0609 ...
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Z80230 Interface Timing Z80230 Write Cycle Timing The Z-Bus compatible ESCC is suited for system applications with multiplexed address/ data buses. Two control signals, AS and DS, are used by the Z80230 to control bus transactions. Addi- tionally, four other ...
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Z80230 Read Cycle Timing The Read Cycle Timing for the Z80230 is displayed in A7-A0, as well as the state of CS0 and INTACK, are latched by the rising edge of AS. R/W must be High before DS falls to ...
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A7-A0. WR9 bit 1 is set disable the placing of a vector on a bus. The INT pin also goes inactive in response to the falling edge of DS. There is only one DS per ...
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the first transaction involving the ESCC, to the fall- ing edge the second transaction. This time must be at least four PCLKs regardless of which register ...
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A/B, D/C INTACK CE D7–D0 WR Figure 21. Write Cycle Timing (Z85230/L) Z85230/L Interrupt Acknowledge Cycle Timing Figure 22 displays Interrupt Acknowledge Cycle timing. Between the time INTACK goes Low and the falling edge of RD, the internal and external ...
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Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in this section can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition above those indicated in the operational section ...
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Figure 23 displays typical test load configurations. From Output Under Test 100pf Standard Test Load Figure 23. Standard and Open-Drain Test Loads Capacitance Table 41 lists the capacitance parameters and contains the symbols and test conditions for each. Table 41. ...
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DC Characteristics Table 42 lists the DC characteristics for the Z80230/Z85230 device. Table 42. Z80230/Z85230 DC Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Output High Voltage 2.4 OH1 V Output High Voltage V ...
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Table 43 lists the DC characteristics for the Z8523L device. Table 43. Z8523L DC Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Output High Voltage 2.4 OH1 V Output High Voltage V OH2 V ...
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AS 1 CS0 3 4 CS1 INTACK 7 R/W Read W/R Write DS AD7-AD0 Write 15 16 AD7-AD0 Read 15 16 W/REQ Wait W/REQ Request DTR/REQ Request INT PCLK Figure 24. Z80230 Read/Write Timing Diagram PS005308-0609 5 ...
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Figure 25 displays the Z80230 Interrupt Acknowledge timing diagram AS INTACK DS AD7-AD0 IEI 34 IEO INT Figure 25. Z80230 Interrupt Acknowledge Timing Diagram Figure 26 displays the Z80230 Reset timing diagram Figure 26. Z80230 Reset Timing ...
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Figure 27 displays the Z80230 general timing diagram. PCLK W/REQ Request W/REQ Wait CTS/TRxC, RTxC Receive 4 RxD 8 SYNC External CTS/TRxC, RTxC Transmit TxD CTS/TRxC Output RTxC CTS/TRxC CTS/TRxC, DCD SYNC Input Figure 27. Z80230 General Timing Diagram PS005308-0609 ...
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Table 44 lists the Z80230 general timing characteristics details. Table 44. Z80230 General Timing Characteristics No. Symbol Parameter 1 TdPC (REQ) PCLK Low to W/REQ Valid 2 TsPC (W) PCLK Low to Wait Inactive 3 TsRXC (PC) RxC High to ...
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Table 44. Z80230 General Timing Characteristics (Continued) No. Symbol Parameter Notes: 1. RxC is RTxC or TRxC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC ...
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Table 45. Z80230 AC Characteristics (Continued) No Symbol Parameter 13 TwDSI DS Low Width 14 TrC Valid Access Recovery Time 15 TsA (AS) Address to AS Rise Setup Time 16 ThA (AS) Address to AS Rise Hold Time 17 TsDW ...
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... Parameter is system-dependent. For any Zilog ESCC in the daisy chain. TdAS (DSA) must be greater than the sum of TdAS (IEO) for the highest priority device in the daisy chain. TsIEI (DSA) for the Zilog ESCC, and TdIEI (IEO) for each device separating them in the daisy chain. ...
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Figure 28 displays the Z80230 system timing diagram. RTxC,TRxC Receive W/REQ Request W/REQ Wait SYNC Output INT TRxC,RTxC Transmit W/REQ Request W/REQ Wait DTR/REQ Request INT CTS,DCD SYNC Input INT Figure 28. Z80230 System Timing Diagram PS005308-0609 Product Specification 1 ...
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Table 46 lists the Z80230 system timing parameter details. Table 46. Z80230 System Timing Table No. Symbol Parameter 1 TdRXC (REQ) RxC High to W/REQ Valid 2 TdRXC (W) RxC High to Wait Inactive 3 TdRXC (SY) RxC High to ...
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PCLK 6 A/B, D/C 8 INTACK D7–D0 Read WR D7–D0 Write W/REQ Wait W/REQ Request DTR/REQ Request INT Figure 29. Z85230/L Read/Write Timing Diagram PS005308-0609 Active Valid 23 24 ...
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Figure 30. Z85230/L Reset Timing Diagram PCLK INTACK 7–D0 IEI 43 IEO INT Figure 31. Z85230/L Interrupt Acknowledge Timing Diagram Figure 32. Z85230/L Cycle Timing Diagram PS005308-0609 48 38 ...
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Table 47 lists the Z85230/L Read and Write AC characteristics details. Table 47. Z85230/L AC Characteristics (20MHz applies only to Z85230) No Symbol Parameter 1 TwPCl PCLK Low Width 2 TxPCh PCLK High Width 3 TfPC PCLK Fall Time 4 ...
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Table 47. Z85230/L AC Characteristics (20MHz applies only to Z85230) (Continued) No Symbol Parameter 18 TsCEh (WR) CE High to WR Fall Setup Time 19 TsCEI (RD) CE Low to RD Fall Setup Time 20 ThCE ((RD ...
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Table 47. Z85230/L AC Characteristics (20MHz applies only to Z85230) (Continued) No Symbol Parameter 35a TdWRr WR Fall to DTR/ (REQ) REQ Not Valid 35b TdWRr WR Fall to DTR/ (REQ) REQ Not Valid 36 TdRDr RD Rise to DTR/ ...
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Table 47. Z85230/L AC Characteristics (20MHz applies only to Z85230) (Continued) No Symbol Parameter 49 Trc Valid Access Recovery Time Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Parameter applies only between transactions involving the ESCC. 3. ...
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Figure 33 displays the Z85230/L General Timing Diagram PCLK W/REQ Request W/REQ Wait RTxC,TRxC Receive 4 RxD 8 SYNC External TRxC,RTxC Transmit TxD 13 TRxC Output RTxC TRxC CTS,DCD SYNC Input Figure 33. Z85230/L General Timing Diagram PS005308-0609 3 5 ...
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Table 48 lists the Z85230/L general timing characteristics details. the Z85230/L Read/Write Timing characteristics details. Table 48. Z85230/L General Timing Table (20MHz applies only to Z85230) No Symbol Parameter 1 TdPC (REQ) PCLK to W/REQ Valid 2 TdPC (W) PCLK ...
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Table 48. Z85230/L General Timing Table (20MHz applies only to Z85230) (Continued) No Symbol Parameter 16a TcRTX RTxC Cycle Time 16b TxRX (DPLL) DPLL Cycle Time Min. 17 TcRTXX Crystal Osc. Period 18 TwRTXh TRxC High Width 19 TwTRXI TRxC ...
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Figure 34 displays the Z85230/L System Timing Diagram. Z85230/L System Timing Characteristics. RTxC,TRxC Receive W/REQ Request W/REQ Wait SYNC Output INT RTxC,TRxC Transmit W/REQ Request W/REQ Wait DTR/REQ Request INT CTS,DCD SYNC Input INT Figure 34. Z85230/L System Timing Diagram ...
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Table 49. Z85230/L System Timing Characteristics (20MHz applies only to Z85230) No Symbol Parameter 1 TdRXC RxC to W/REQ (REQ) Valid 2 TdRXC (W) RxC to Wait Inactive 3 TdRXC (SY) RxC to SYNC 2 Valid 4 TdRXC (INT) RxC ...
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... Z80230/Z85230/L Errata The current revision of Zilog’s ESCC has six known bugs. This section identifies these bugs and provides workarounds. IUS Problem Description The IUS problem occurs under the following conditions: • SDLC 10x19 Status FIFO is enabled • Interrupts on Receive Special Conditions only This mode is intended for an application where received characters are read by a DMA controller ...
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The processor does not acknowledge this interrupt because it is servicing another interrupt. • The processor finishes servicing the other interrupt and uses the command. • The IP bit reset corresponding to the EOF, and the EOF interrupt is ...
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Figure 35 displays the procedure for resetting highest IUS. INT Ext/Status IP RCA IP Ext/Status IUS Resetting highest IUS from lower priority interrupt clears the EOF (RCA) interrupt. Figure 35. Resetting Highest IUS from Lower Priority RTS Problem Description The ...
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Enable the CRC/Flag on Underrun (WR10 bit 2 equals 0). 3. Issue a Deactivate RTS deactivates automatically after the closing flag disappears. The Automatic RTS Deactivation consecutive frames back-to-back. This command does not work with more than two back- ...
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The TxD output is automatically forced High for eight bit-times and the first byte of the second frame is corrupted multiple-frame transmission, a zero (0) bit is inserted before the opening flag of the ...
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Default RR10 Value Problem Description RR10 bit 6, the 2 clock missing bit, is sometimes erroneously set to indicate that the DPLL detects a clock edge in two successive tries after hardware reset. Default RR10 Value Problem Solution Ignore the ...
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Package Information Figure 37 displays the 40-pin Dual-Inline Package (DIP Figure 37. 40-Pin DIP Package Diagram PS005308-0609 SYMBOL A1 0. 1.02 B1 ...
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Figure 38 displays the 44-pin Plastic Leaded Chip Carrier (PLCC) package 45° NOTES: 1. CONTROLLING DIMENSION : INCH 2. LEADS ARE COPLANAR WITHIN 0.004". 3. DIMENSION : MM INCH Figure 38. 44-Pin PLCC ...
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... Ordering Information Order the required ESCC from Zilog using the following part details. For more informa- tion on ordering, consult your local Zilog sales offices. The Zilog website (www.zilog.com) lists all the regional offices and provides additional product information. Z8523L (3.3V) Z8523L Available Packages ...
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... Z8023016PSG Z8023016VSG Environmental Flow G = Green Plastic Packaging Compound Temperature E = -40C to +100 0C to +70C Package P = Plastic DIP (PDIP Plastic LCC (PLCC) Speed 8 = 8.0 MHz 10 = 10.0 MHz 16 = 16.384 MHz MHz Product Number Zilog Prefix Z80230/Z85230/L Product Specification 108 Ordering Information ...
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... For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS005308-0609 ...
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Index A 18 abort character 75 absolute maximum ratings 78 AC characteristics AC characteristics table, Z85230 87 AC characteristics, Z85230 4 asynchronous receive mode 21 auto echo and logical loopback 4 auto enable 28 automatic EOM reset B 19 baud ...
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Z80230 pin assignments 2 Z80230 pin functions 3 Z85230 pin assignments 2 Z85230 pin functions 5, 19 digital phase-locked loop 27 DPLL counter Tx clock source E 20 encoding, data 18 end of poll (EOP) ...
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SDLC loop 19 SDLC status FIFO 16 synchronous 4, 16 monosync vector (NV 107 ordering information P 105 package information 108 part number descriiption pin assignments 3 Z80230 3 Z85230 1 pin descriptions ...
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S SDLC 17 CRC polynomial FIFO frame status enhancement 18 loop mode 26 mode, CRC reception 26 mode, TxD forced high 19 status FIFO status FIFO anti-lock feature transmit data interrupt response SDLC FIFO overflow problem 103 description 103 solutions ...