DS21Q42T Maxim Integrated Products, DS21Q42T Datasheet - Page 35

• Manufacturer Part Number: DS21Q42T
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
(MSB)
SYMBOL
SYMBOL
TJC
TCM4
TCM3
TCM2
TCM1
TCM0
TPCSI
TIRFS
THSE
TJC
–
–
–
POSITION
POSITION
CCR4.2
CCR4.1
CCR4.0
CCR5.7
CCR5.6
CCR5.5
CCR5.4
CCR5.3
CCR5.2
CCR5.1
CCR5.0
–
NAME AND DESCRIPTION
Transmit Hardware Signaling Insertion Enable. See Section 10
for details.
0 = do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin.
1 = Insert the signaling from the TSIG pin into data stream
presented at the TSER pin.
Transmit Per–Channel Signaling Insert. See Section 10 for
details.
0 = do not use TCHBLK to determine which channels should have
signaling inserted from the TSIG pin.
1 = use TCHBLK to determine which channels should have
signaling inserted from the TSIG pin.
Transmit Idle Registers (TIR) Function Select. See Section 11
for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e.,
Per = Channel Loopback function)
NAME AND DESCRIPTION
Transmit Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Not Assigned. Must be set to zero when written.
Not Assigned. Must be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode that
determines which transmit channel data will appear in the TDS0M
register. See Section 9 for details.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
TCM4
35 of 116
TCM3
TCM2
TCM1
TCM0
(LSB)