DS21Q42T Maxim Integrated Products, DS21Q42T Datasheet - Page 84

IC FRAMER ENHANCED T1 4X 128TQFP

DS21Q42T

Manufacturer Part Number
DS21Q42T
Description
IC FRAMER ENHANCED T1 4X 128TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q42T

Controller Type
T1 Framer
Interface
Parallel/Serial
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Table 19-3. DEVICE ID CODES
HIGH-Z
All digital outputs of the DS21Q42 will be placed in a high impedance state. The BYPASS register will
be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS21Q42 will output data from the boundary scan parallel output while
connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP
instruction.
19.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21Q42 design.
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 126 bits in length. Table 17-3 shows all of the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state.
DS21Q42
DS21Q44
DEVICE
16-BIT NUMBER
0000h
0001h
84 of 116
This test register is the

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