DS3148N Maxim Integrated Products, DS3148N Datasheet - Page 57
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DS3148N
Manufacturer Part Number
DS3148N
Description
IC 8CH DS3/3 FRAMER 349-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3148.pdf
(89 pages)
Specifications of DS3148N
Controller Type
DS3/E3 Framer
Interface
LIU
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
640mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
349-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: Transmit Low Watermark Select Bits (TLWMS[2:0]). These control bits determine when the HDLC
controller should set the TLWM status bit in the
number of bytes specified by these bits, the TLWM status bit is set to logic 1.
Bits 4 to 6: Receive High Watermark Select Bits (RHWMS[2:0]). These control bits determine when the HDLC
controller should set the RHWM status bit in the
number of bytes specified by these bits, the RHWM status bit is set to logic 1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: Transmit FIFO Low Watermark (TLWM). This real-time status bit is set to a 1 when the transmit FIFO
contains less than the number of bytes configured by TLWMS[2:0] control bits in the
cleared when the FIFO fills beyond the low watermark.
Bit 3: Receive FIFO High Watermark (RHWM). This real-time status bit is set to a 1 when the receive FIFO
contains more than the number of bytes configured by the RHWMS[2:0] control bits in the
cleared when the FIFO empties below the high watermark.
RHWMS[2:0]
TLWMS[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
N/A
—
7
N/A
—
7
RHWMS2
TRANSMIT LOW WATERMARK (BYTES)
RECEIVE HIGH WATERMARK (BYTES)
6
0
N/A
—
6
HSR
HDLC Status Register
54h
HCR2
HDLC Control Register 2
51h
RHWMS1
N/A
112
144
176
208
240
112
144
176
208
240
5
0
—
16
48
80
16
48
80
5
RHWMS0
HSR
HSR
57 of 89
N/A
—
4
4
0
register. When the transmit FIFO contains less than the
register. When the receive FIFO contains more than the
N/A
RHWM
—
3
—
3
TLWMS2
2
0
TLWM
—
2
TLWMS1
HCR2
HCR2
1
0
N/A
—
1
register. This bit is
register. This bit is
TLWMS0
N/A
0
0
—
0