DS3148N Maxim Integrated Products, DS3148N Datasheet - Page 67
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DS3148N
Manufacturer Part Number
DS3148N
Description
IC 8CH DS3/3 FRAMER 349-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3148.pdf
(89 pages)
Specifications of DS3148N
Controller Type
DS3/E3 Framer
Interface
LIU
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
640mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
349-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 5: Transmit FEAC Codeword A Data (TFCA[5:0]). The FEAC codeword is of the form
…0xxxxxx011111111… where the rightmost bit is transmitted first. TFCA[5:0] are the middle six bits of the second
byte of the FEAC codeword (i.e., the six “x” bits). The transmit FEAC controller can generate two different
codewords. These six bits specify what is to be transmitted for codeword A. TFCA0 is the LSB and is transmitted
first; TFCA5 is the MSB and is transmitted last. The TFS[1:0] control bits determine if this codeword is to be
transmitted. These bits should only be changed when the transmit FEAC controller is in the idle state (TFS[1:0] =
00).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 5: Transmit FEAC Codeword B Data (TFCB[5:0]). The FEAC codeword is of the form
…0xxxxxx011111111… where the right-most bit is transmitted first. TFCB[5:0] are the middle six bits of the second
byte of the FEAC codeword (i.e., the six “x” bits). The transmit FEAC controller can generate two different
codewords. These six bits specify what is to be transmitted for codeword B. TFCB0 is the LSB and is transmitted
first; TFCB5 is the MSB and is transmitted last. The TFS[1:0] control bits determine if this codeword is to be
transmitted. These bits should only be changed when the transmit FEAC controller is in the idle state
(TFS[1:0] = 00).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 5: Receive FEAC FIFO Data (RFF[5:0]). Data from the receive FEAC FIFO can be read from these bits.
The FEAC codeword is of the form …0xxxxxx011111111… where the right-most bit is received first. These six bits
are the debounced and integrated middle six bits of the second byte of the FEAC codeword (i.e., the six “x” bits).
RFF0 is the LSB and is received first; RFF5 is the MSB and is received last.
N/A
N/A
N/A
—
—
—
7
7
7
N/A
N/A
N/A
—
—
—
6
6
6
TFEACA
Transmit FEAC A
64h
TFEACB
Transmit FEAC B
65h
RFEAC
Receive FEAC
66h
TFCA5
TFCB5
RFF5
—
5
0
5
0
5
TFCA4
TFCB4
67 of 89
RFF4
—
0
0
4
4
4
TFCA3
TFCB3
RFF3
—
3
0
3
0
3
TFCA2
TFCB2
RFF2
—
2
0
2
0
2
TFCA1
TFCB1
RFF1
—
1
0
1
0
1
TFCA0
TFCB0
RFF0
—
0
0
0
0
0