ISP1581BD ST-Ericsson Inc, ISP1581BD Datasheet - Page 26

• Manufacturer Part Number: ISP1581BD
• Description: IC USB PERIPHERAL CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1581BD

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 130mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1172; ISP1581BD,557

Philips Semiconductors
Table 19:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Data Port register: bit allocation
15
7
9.3.4 Buffer Length register (address: 1CH)
Remark: The buffer can be validated or cleared automatically by using the Buffer
Length register (see
Table 20:
This 2-byte register determines the current packet size (DATACOUNT) of the indexed
endpoint FIFO. The bit allocation is given in
The Buffer Length register is automatically loaded with the FIFO size, when the
Endpoint MaxPacketSize register is written (see
written when required. After a bus reset the Buffer Length register is made zero.
IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not significant. This register is useful only when transferring
data that is not a multiple of MaxPacketSize. The following two examples
demonstrate the significance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be filled. This is
because the transfer size is a multiple of MaxPacketSize, and the MaxPacketSize
packets will be automatically validated because the last packet is also of
MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register should be filled with 62 bytes just
before the MCU writes the last packet of 62 bytes. This ensures that the last packet,
which is a short packet of 62 bytes, is automatically validated.
This is only applicable to the PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of
data bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized
packet is output as the lower byte (LSByte).
Bit
15 to 8
7 to 0
14
6
Data Port register: bit description
Symbol
DATAPORT[15:8]
DATAPORT[7:0]
13
5
Rev. 06 — 23 December 2004
Table
21).
DATAPORT[15:8]
12
DATAPORT[7:0]
4
Description
data (upper byte); not used in 8-bit bus mode
data (lower byte)
R/W
R/W
00H
00H
00H
00H
11
3
Table
Hi-Speed USB peripheral controller
Table
21.
10
2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
22). A smaller value can be
9
1
ISP1581
8
0
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