ISP1581BD ST-Ericsson Inc, ISP1581BD Datasheet - Page 28

• Manufacturer Part Number: ISP1581BD
• Description: IC USB PERIPHERAL CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1581BD

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 130mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1172; ISP1581BD,557

Philips Semiconductors
Table 24:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Endpoint Type register: bit allocation
R/W
15
7
-
-
-
-
9.3.6 Endpoint Type register (address: 08H)
9.3.7 Short Packet register (address: 24H)
This register sets the Endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and configure it for double buffering.
Automatic generation of an empty packet for a zero length TX buffer can be disabled
via bit NOEMPKT. The register contains 2 bytes and the bit allocation is shown in
Table
reserved
Table 25:
This register is reserved.
Bit
15 to 5
4
3
2
1 to 0
R/W
14
6
-
-
-
-
24.
Symbol
reserved
NOEMPKT
ENABLE
DBLBUF
ENDPTYP[1:0]
Endpoint Type register: bit description
R/W
13
5
-
-
-
-
Rev. 06 — 23 December 2004
NOEMPKT
Description
reserved.
No Empty Packet: A logic 0 causes an empty packet to be
appended to the next IN token of the USB data, if the Buffer
Length register or the Endpoint MaxPacketSize register is zero.
A logic 1 disables this function. This bit is applicable only in
DMA mode.
Endpoint Enable: A logic 1 enables the FIFO of the indexed
endpoint. The memory size is allocated as specified in the
Endpoint MaxPacketSize register. A logic 0 disables the FIFO.
Note: ‘Stalling’ a data endpoint will confuse the Data Toggle bit
on the stalled endpoint because the internal logic picks up from
where it has stalled. Therefore, the Data Toggle bit must be
reset by disabling and re-enabling the corresponding endpoint
(by setting the bit ‘ENABLE’ to 0 or 1 in the endpoint type
register) to reset the PID.
Double Buffering: A logic 1 enables double buffering for the
indexed endpoint. A logic 0 disables double buffering.
Endpoint Type: These bits select the endpoint type as follows:
01H — isochronous
02H — bulk
03H — interrupt.
R/W
12
4
0
0
-
-
reserved
R/W
ENABLE
R/W
11
3
0
0
-
-
Hi-Speed USB peripheral controller
DBLBUF
R/W
10
2
0
0
-
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9
1
-
-
ENDPTYP[1:0]
ISP1581
00H
00H
R/W
8
0
27 of 79
-
-