SJA1000T/N,112 NXP Semiconductors, SJA1000T/N,112 Datasheet - Page 16

• Manufacturer Part Number: SJA1000T/N,112
• Description: IC STAND-ALONE CAN CTRLR 28-SOIC
• Manufacturer: NXP Semiconductors

Specifications of SJA1000T/N,112

• Controller Type: CAN Interface
• Interface: CAN
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277294112; SJA1000T/N; SJA1000T/N

Philips Semiconductors
Notes
1. When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the
2. Errors detected during reception or transmission will affect the error counters according to the CAN 2.0B protocol
3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle.
4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit is set to
5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is at logic 0 (locked), the written byte
6. When a message that shall be received has passed the acceptance filter successfully (i.e. earliest after arbitration
7. After reading a message stored in the RXFIFO and releasing this memory space with the command release receive
2000 Jan 04
Stand-alone CAN controller
CAN controller will set the reset request bit to logic 1 (present) and an error interrupt is generated, if enabled. It will
stay in this mode until the CPU clears the reset request bit. Once this is completed the CAN controller will wait the
minimum protocol-defined time (128 occurrences of the bus-free signal). After that the bus status bit is cleared
(bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error interrupt is generated, if
enabled.
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit of 96. An error interrupt is generated, if enabled.
logic 1. The transmission complete status bit will remain at logic 0 (incomplete) until a message is transmitted
successfully.
will not be accepted and will be lost without being indicated.
field), the CAN controller needs space in the RXFIFO to store the message descriptor. Accordingly there must be
enough space for each data byte which has been received. If there is not enough space to store the message, that
message will be dropped and the data overrun condition will be indicated to the CPU only, if this received message
has no errors until the last but one bit of end of frame (message becomes valid).
buffer, this bit is cleared. If there is another message available within the FIFO this bit is set again with the next bit
quantum (t
scl
).
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Product specification
SJA1000