S-8233AKFT-TB-G Seiko Instruments, S-8233AKFT-TB-G Datasheet - Page 14

• Manufacturer Part Number: S-8233AKFT-TB-G
• Description: Battery Management Lithium-Ion battery protection (3 cell)
• Manufacturer: Seiko Instruments

Specifications of S-8233AKFT-TB-G

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Overdischarge status
Delay circuits
CTL pin
0 V battery charging function
If any one of the battery voltages falls below the overdischarge detection voltage (V
under normal status and it continues for the overdischarge detection delay time (t
discharging FET turns off and discharging stops. This status is called the overdischarge status. When
the discharging FET turns off, the VMP pin voltage becomes equal to the VSS voltage and the IC's
current consumption falls below the power-down current consumption (I
power-down status. The VMP and VSS pins are shorted by the R
and power-down statuses.
The overcharge detection delay time (t
overcurrent detection delay time 1 (t
The delay times are calculated by the following equations:
If the CTL pin is floated under normal status, it is pulled up to the V
charging and discharging FETs turn off to inhibit charging and discharging.
discharging are also inhibited by applying the VCC pin to the CTL pin externally. At this time, the VMP
and VCC pins are shorted by the R
This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V.
When the 0 V charging start voltage (V
the charger, the charging FET gate is fixed to V
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the overdischarge release
voltage (V
The power-down status is canceled when the charger is connected and the voltage between VMP and
VSS is 3.0 V or higher (overcurrent detection voltage 3). When all the battery voltages becomes equal to
or higher than the overdischarge release voltage (V
the normal status.
When the CTL pin becomes equal to V
their appropriate statuses for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
Caution In the products without 0 V battery charging function, the resistance between VCC and
Caution The delay time for overcurrent detection 2 and 3 is fixed by an internal IC circuit. The
t
t
t
CU
DD
IOV1
[s] = Delay factor ( 1.07, 2.13, 3.19)×C4 [μF]
[s] = Delay factor ( 0.20, 0.40, 0.60)×C5 [μF]
[s] = Delay factor ( 0.10, 0.20, 0.30)×C6 [μF]
VMP and between VSS and VMP are lower than the products with 0 V battery charging
function. It causes to that overcharge detection voltage increases by the drop voltage of
R5 (see Figure 10) with sink current at VMP.
The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0
V battery charging function.
between the CTL pin ('L' level) and VSS is generated through the external filter (R
C
DU
delay time cannot be changed via an external capacitor.
VSS
), the normal status returns.
) as a result of input voltage fluctuations.
Min. Typ.
VCM
Max.
IOV1
Seiko Instruments Inc.
resistor.
0CHAR
) are changed with external capacitors (C4 to C6).
SS
CU1
potential, charging and discharging are enabled and go back to
to t
) or higher is applied to between VMP and VSS by connecting
CU3
SS
), overdischarge detection delay time (t
potential.
DU
) in this status, the overdischarge status changes to
VSM
CC
resistor under the overdischarge
potential in the IC, and both the
PDN
). This status is called the
DD
Both charging and
) during discharging
DD
) or longer, the
DD1
Rev.6.0
to t
DD3
VSS
), and
_00
and