78M6612-IMR/F/PD2 Maxim Integrated Products, 78M6612-IMR/F/PD2 Datasheet - Page 82
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78M6612-IMR/F/PD2
Manufacturer Part Number
78M6612-IMR/F/PD2
Description
Current & Power Monitors & Regulators 2 Out Sgl Phase Pwr & Energy Msrmt IC
Manufacturer
Maxim Integrated Products
Datasheet
1.78M6612-IMF.pdf
(111 pages)
Specifications of 78M6612-IMR/F/PD2
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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78M6612 Data Sheet
82
Name
WAKE_ARM
WAKE_PRD
WAKE_RES
WD_RST
WD_OVF
WE
Location
20A9[2:0]
SFRE8[7]
201F[7:0]
20A9[7]
20A9[3]
2002[2]
Rst
001
0
0
0
0
–
Wk
–
–
–
0
0
–
Dir
R/W
R/W
R/W
W
W
W
Description
Arm the autowake timer. Writing a 1 to this bit arms the
autowake timer and presets it with the values presently in
WAKE_PRD and WAKE_RES. The autowake timer is reset
and disarmed whenever the MPU is in MISSION mode or
BROWNOUT mode. The timer must be armed at least
three RTC cycles before the SLEEP or LCD-ONLY mode
is commanded.
Sleep time. Time=WAKE_PRD[2:0]*WAKE_RES.
Default=001. Maximum value is 7.
Resolution of WAKE timer: 1 – 1 minute, 0 – 2.5
seconds.
WD timer bit: Possible operations to this bit are:
Read: Gets the status of the flag IE_PLLFALL
Write 0: Clears the flag.
Write 1:.Resets the WDT.
The WD overflow status bit. This bit is set when the WD
timer overflows. It is powered by the non-volatile supply
and at bootup will indicate if the part is recovering from a
WD overflow or a power fault. This bit should be cleared
by the MPU on bootup. It is also automatically cleared
when RESET is high.
Write operations on the RTC registers must be preceded
by a write operation to WE.
DS_6612_001
Rev. 1.2
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