CY7C63913-PXC Cypress Semiconductor Corp, CY7C63913-PXC Datasheet - Page 30

• Manufacturer Part Number: CY7C63913-PXC
• Description: IC USB PERIPHERAL CTRLR 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63913-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
14.2.10 P0.0/CLKIN Configuration
Table 14-6. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
14.2.11 P0.1/CLKOUT Configuration
Table 14-7. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
This pin is shared between the P0.0 GPIO use and the CLKIN pin for the external crystal oscillator. When the external oscillator
is enabled the settings of this register are ignored
The use of the pin as the P0.0 GPIO is available in all the enCoRe II parts. The alternate function of the pin as the CLKIN is only
available in the CY7C639xx. When the external oscillator is enabled (the XOSC Enable bit of the CLKIOCR Register is
set—Table 10-8), the GPIO function of the pin is disabled
The 50-mA sink drive capability is only available in the CY7C639xx. In the CY7C638xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit
This pin is shared between the P0.1 GPIO use and the CLKOUT pin for the external crystal oscillator. When the external oscillator
is enabled the settings of this register are ignored. When CLK output is set, the internally selected clock is sent out onto
P0.1CLKOUT pin.
The use of the pin as the P0.1 GPIO is available in all the enCoRe II parts. The alternate function of the pin as the CLKOUT is
only available in the CY7C639xx. When the external oscillator is enabled (the XOSC Enable bit of the CLKIOCR Register is
set—Table 10-8), the GPIO function of the pin is disabled
The 50-mA sink drive capability is only available in the CY7C639xx. In the CY7C638xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit
Bit 7: CLK Output
0 = The clock output is disabled
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register—Table 10-8) is driven out to the pin
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
CLK Output
Reserved
R/W
7
--
0
7
0
Pull-Up Enable
TTL Threshold
(On Designated
Output Enable
3.3V Drive
Open Drain
High Sink
Pins Only)
Port Data
Int Enable
Int Enable
Data In
R/W
R/W
6
0
6
0
Figure 14-1. Block Diagram of a GPIO
Int Act Low
Int Act Low
R/W
R/W
5
0
5
0
VREG
VREG GND
TTL Thresh
TTL Thresh
R/W
R/W
4
0
4
0
VREG
Vsupply GND
VCC
High Sink
High Sink
R/W
R/W
3
0
3
0
R
UP
Vsupply
Open Drain
Open Drain
R/W
R/W
GPIO PIN
2
0
2
0
Data Out
Pull-up Enable
Pull-up Enable
R/W
R/W
1
0
1
0
CY7C63310
CY7C638xx
CY7C639xx
Page 30 of 68
Output Enable
Output Enable
R/W
R/W
0
0
0
0