CY7C63913-PXC Cypress Semiconductor Corp, CY7C63913-PXC Datasheet - Page 41

• Manufacturer Part Number: CY7C63913-PXC
• Description: IC USB PERIPHERAL CTRLR 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63913-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
16.1.13 Capture Interrupt Status
Table 16-13. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]
17.0
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the enCoRe II devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually. The registers also
provide a mechanism by which a user may clear all pending
and posted interrupts, or clear individual posted or pending
interrupts.
The following table lists all interrupts and the priorities that are
available in the enCoRe II devices.
Table 17-1. Interrupt Numbers, Priorities, Vectors
Bit [7:4]: Reserved
Bit 3: Cap1 Fall Active
0 = No event
1 = A falling edge has occurred on Cap1
Bit 2: Cap1 Rise Active
0 = No event
1 = A rising edge has occurred on Cap1
Bit 1: Cap0 Fall Active
0 = No event
1 = A falling edge has occurred on Cap0
Bit 0: Cap0 Rise Active
0 = No event
1 = A rising edge has occurred on Cap0
Interrupt
Priority
Read/Write
Default
10
11
12
13
14
15
16
Field
Bit #
0
1
2
3
4
5
6
7
8
9
Interrupt Controller
Interrupt
Address
000Ch
001Ch
002Ch
003Ch
0000h
0004h
0008h
0010h
0014h
0018h
0020h
0024h
0028h
0030h
0034h
0038h
0040h
7
–
0
Reset
POR/LVD
INT0
SPI Transmitter Empty
SPI Receiver Full
GPIO Port 0
GPIO Port 1
INT1
EP0
EP1
EP2
USB Reset
USB Active
1-mS Interval timer
Programmable Interval Timer
Timer Capture 0
Timer Capture 1
6
–
0
Reserved
Name
5
–
0
4
–
0
Table 17-1. Interrupt Numbers, Priorities, Vectors (contin-
17.1
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in Figure 17-1 clocking in a ‘1’. The
interrupt will remain posted until the interrupt is taken or until
it is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register).
All pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which will be taken by
the M8C if the Global Interrupt Enable bit is set in the CPU_F
register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor
does it prevent an interrupt from being posted. It simply
prevents a posted interrupt from becoming pending.
Nested interrupts can be accomplished by re-enabling inter-
rupts inside an interrupt service routine. To do this, set the IE
bit in the Flag Register.
A block diagram of the enCoRe II Interrupt Controller is shown
in Figure 17-1.
Interrupt
Priority
17
18
19
20
21
22
23
24
25
Cap1 Fall
Architectural Description
Active
R/W
3
0
Interrupt
Address
004Ch
005Ch
0044h
0048h
0050h
0054h
0058h
0060h
0064h
Cap1 Rise
Active
R/W
16-bit Free Running Timer Wrap
INT2
GPIO Port 2
GPIO Port 3
GPIO Port 4
Reserved
Reserved
Sleep Timer
PS2 Data Low
2
0
Cap0 Fall
Active
R/W
1
0
Name
CY7C63310
CY7C638xx
CY7C639xx
Page 41 of 68
Cap0 Rise
Active
R/W
0
0