DP83257VF National Semiconductor, DP83257VF Datasheet - Page 48
![no-image](/images/manufacturer_photos/0/4/469/national_semiconductor_sml.jpg)
DP83257VF
Manufacturer Part Number
DP83257VF
Description
IC FDDI LAYER CTRLR 160PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83256VF.pdf
(144 pages)
Specifications of DP83257VF
Controller Type
physical layer controller
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Interface
-
Other names
*DP83257VF
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DP83257VF
Manufacturer:
NVIDIA
Quantity:
12 388
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D0 D1
D2
5 0 Registers
5 5 CURRENT TRANSMIT STATE REGISTER (CTSR)
The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle Master Halt
Quiet or user programmable symbol pairs in addition to the normal transmission of incoming PHY Request data The Smoother
and PHY Request Data Parity are also enabled and disabled through this register
When the Trigger Definition register (TDR) is used the CTSR can automatically be set to a preprogrammed line state when a
trigger condition occurs This capability can be used to implement both PC React and CF React
The Transmit Modes have priority over the Repeat Filter and Smoother outputs The Injection Symbols have priority over the
Transmit Modes
During the reset process (i e E RST
is set to 1) and the Reserved bit (b7) is set to 1 All other bits of this register are cleared (i e set to 0) during the reset process
When the TDR register is used to respond to trigger conditions the CTSR will be blocked when the TDR register transmit mode
is copied into the CTSR The Write Reject bit of the ICR will be set if any writes are attempted at this time
Note This register has no effect while the device is in Stop Mode
ACCESS RULES
Bit
RES
ADDRESS
D7
04h
TM0 TM1
TM2
Symbol
PRDPE
D6
Transmit Mode
output port (TXD
TM2
0
0
0
0
1
1
1
1
(Continued)
Always
READ
TM1
0
0
1
1
0
0
1
1
D5
SE
e
TM0
0
1
0
1
0
1
0
1
GND) the Transmit Mode is set to Off (TM
k
g
0 1 2
)
Conditional
Active Transmit Mode (ATM) Normal transmission of incoming PHY Request data
Idle Transmit Mode (ITM) Transmission of Idle symbol pairs (11111 11111)
Off Transmit Mode (OTM) Transmission of Quiet symbol pairs (00000 00000) and
deassertion of the PMD transmitter Enable pin (TXE)
Note This is the default transmit mode after reset
Reserved Reserved for future use Users are discouraged from using this transmit
mode If selected however the transmitter will generate Quiet symbol pairs (00000
00000)
Master Transmit Mode (MTM) Transmission of Halt and Quiet symbol pairs (00100
00000)
Halt Transmit Mode (HTM) Transmission of Halt symbol pairs (00100 00100)
Quiet Transmit Mode (QTM) Transmission of Quiet symbol pairs (00000 00000)
Reserved Reserved for future use Users are discouraged from using this transmit
mode If selected however the transmitter will generate Quiet symbol pairs
(00000 00000)
WRITE
IC1
D4
l
These bits select one of the 6 transmission modes for the PMD Request Data
IC0
D3
48
Description
TM2
D2
k
2 0
l
TM1
D1
e
010) the Smoother is enabled (i e SE
TM0
D0
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