DP83257VF National Semiconductor, DP83257VF Datasheet - Page 59
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DP83257VF
Manufacturer Part Number
DP83257VF
Description
IC FDDI LAYER CTRLR 160PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83256VF.pdf
(144 pages)
Specifications of DP83257VF
Controller Type
physical layer controller
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Interface
-
Other names
*DP83257VF
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83257VF
Manufacturer:
NVIDIA
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D0-D7
5 0 Registers
5 15 NOISE PRESCALE THRESHOLD REGISTER (NPTR)
The Noise Prescale Threshold Register contains the start value for the Noise Prescale Timer This threshold register is used in
conjunction with the Noise Threshold register for setting the maximum allowable time between entry to ILS HLS MLS ALS or
NSD The Noise timer is used to implement the TNE timing requirement of PCM The Noise Prescale threshold controls how
often the Noise timer is decremented When the Noise Prescale Timer reaches zero it reloads the count with the contents of the
Noise Prescale Threshold Register and also causes the Noise Timer to decrement
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true
1 Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State Active
or
2 The Current Line State is either Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect
or
3 The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle
In addition the value of the Noise Prescale Threshold Register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero
The Noise Counter and Noise Prescale Counter will continue to count without resetting or reloading the threshold values if a
Line State change occurs and the new line state is either Noise Line State Active Line State or Line State Unknown
When both the Noise Threshold Counter and Noise Counter both reach zero the Noise Threshold bit of the Receive Condition
Register A will be set
See the NTR register description for default value recommendations
ACCESS RULES
Bit
Line State or Line State Unknown
NPT7
D7
ADDRESS
NPT0-NPT7
0Eh
Symbol
NPT6
D6
NOISE PRESCALE THRESHOLD BIT
NPT0 is the Least Significant Bit (LSB)
(Continued)
Always
READ
NPT5
D5
NPT4
D4
WRITE
Always
NPT3
D3
k
59
0-7
l
Description
Start value for the Noise Prescale Timer
NPT2
D2
NPT1
D1
NPT0
D0
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