DP83257VF National Semiconductor, DP83257VF Datasheet - Page 68

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 24 USER DEFINABLE REGISTER (UDR)
The User Definable Register is used to monitor and control events which are external to the PLAYER
The value of the Sense Bits reflect the asserted deasserted state of their corresponding Sense pins On the other hand the
Enable bits assert deassert the Enable pins
Note SB2 and EB2 are only effective for the DP83257
ACCESS RULES
RES
Symbol
SB0
SB1
EB0
EB1
SB2
RES
EB2
RES
D7
ADDRESS
17h
SENSE BIT 0 This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (i e SP0
time Once the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus Interface even
if the signal is deasserted This ensures that the Control Bus Interface will record the source of events which can
cause interrupts in a traceable manner
SENSE BIT 1 This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (i e SP1
time Once the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus Interface even
if the signal is deasserted This ensures that the Control Bus Interface will record the source of events which can
cause interrupts in a traceable manner
ENABLE BIT 0 The Enable Bit 0 allows control of external logic through the Control Bus Interface The User
Definable Enable Pin 0 (EP0) is asserted deasserted by this bit
0
1
ENABLE BIT 1 This bit allows control of external logic through the Control Bus Interface The User Definable
Enable Pin 0 (EP0) is asserted deasserted by this bit
0
1
SENSE BIT 2 This bit is set to 1 if the Sense Pin 2 (SP2) is asserted (i e SP2
time Once the asserted signal is latched Sense Bit 2 can only be cleared through the Control Bus Interface even
if the signal is deasserted This ensures that the Control Bus Interface will record the source of events which can
cause interrupts in a traceable manner
Note SB2 and EB2 are only effective for the DP83257
RESERVED Reserved for future use The reserved bit is set to 0 during the initialization process
(i e E RST
Note Users are discouraged from using this bit It may be set or cleared without any effects to the functionality of the PLAYER
ENABLE BIT2 The Enable Bit 2 allows control of external logic through the Control Bus Interface The User
Definable Enable Pin 2 (EP2) is asserted deasserted by this bit
Note SB2 and EB2 are only effective for the DP83257
0
1
RESERVED Reserved for future use The reserved bit is set to 0 during the initialization process
(i e E RST
Note Users are discouraged from using this bit It may be set or cleared without any effects to the functionality of the PLAYER
EB2
D6
EP0 is deasserted (i e EP0
EP0 is asserted (i e EP0
EP1 is deasserted (i e EP1
EP1 is asserted (i e EP1
EP2 is deasserted (i e EP2
EP2 is asserted (i e EP2
(Continued)
e
e
Always
READ
GND)
GND)
RES
D5
SB2
e
e
e
D4
WRITE
Always
V
V
V
e
e
e
CC
CC
CC
GND)
GND)
GND)
)
)
)
EB1
D3
68
Description
EB0
D2
SB1
D1
e
e
e
V
V
V
CC
CC
CC
) for a minimum amount of
) for a minimum amount of
) for a minimum amount of
SB0
D0
a
device
a
a
device
device