DP83907VF National Semiconductor, DP83907VF Datasheet - Page 12

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

4 0 Functional Description
The ISA standard determines that within 500 ns of RESET
going active all devices should enter the appropriate reset
condition The DP83907 will generate the internal signal
IOinactive after RESET has been active for 400 ns which
will disable all outputs and cause RESET to be the only
input monitored The DP83907 will not respond to a RESET
pulse of shorter duration than this An internal timer contin-
ues to monitor the amount of time RESET is active After
415
ternal signal called RegLoad is generated
When a Power-On-Reset occurs the DP83907 latches in the
values on the configuration pins and uses these to configure
the internal registers and options Internally these pins con-
tain pull-down resistors which are enabled when IOinactive
goes active If any pins are unconnected they default to a
logic zero The intemal pull-down resistor has a high resist-
ance to allow the external pull-up resistors to be of a high
value This limits the current taken by the memory support
bus The suggested external resistor value is 10 k
configuration registers are loaded from the memory support
bus when RESET goes inactive if RegLoad is active The
internal pull-down resistors are enabled onto the bus until
RegLoad has gone inactive
A Power-On-Reset also causes the DP83907 to load the
internal PROM space from the EEPROM which can take up
to 320
The DP83907 will be inaccessible during this time If
EECONFIG is held high the configuration data loaded on
the falling edge of RESET will be overwritten with data read
from the serial EEPROM Regardless of the level on
EECONFIG the PROM space will always be loaded with
data from the serial EEPROM during the time specified
as EELoad
4 3 EEPROM OPERATION
The DP83907 uses an NMC93C06 or another serial
EEPROM with compatible timings The NMC93C06 is a 256-
bit device arranged as 16 words by 16 bits wide The pro-
grammed contents of the EEPROM is shown in Figure 7
0Fh
0Eh
08h
07h
03h
02h
01h
00h
s it is considered a valid Power-On-Reset and an in-
FIGURE 7 EEPROM Programming Map
s This occurs after RegLoad has gone inactive
D15
E’net Address 5
E’net Address 3
E’net Address 1
EEPROM Code
Reserved
Config B
42h
57h
E’net Address 4
E’net Address 2
E’net Address 0
Reserved
Config C
Config A
(Continued)
42h
57h
D0
The
12
Mapping EEPROM into PROM Space
Data is read from the EEPROM at boot time and stored in
registers within the DP83907 While this operation takes
place the DP83907 can not be accessed by the system
These registers are mapped into the space traditionally oc-
cupied by the PROM in the NE2000
The user should program the EEPROM to contain the Ether-
net address in the first six bytes and whatever is required in
the next 8 bytes The user should then program 5757H and
4242H into address 07h and 08h respectively
DP83907 device driver may determine that this is a 16-bit
board by checking this value
The DP83907 reads the first 8 words from the EEPROM and
maps them into the memory map at the appropriate ad-
dress
In Circuit ProgrammIng the EEPROM
If the upper byte of address 0Fh in the EEPROM does not
contain 073H then the DP83907 enters a mode that allows
the EEPROM contents to be programmed This can be used
in production to program the EEPROM in-situ By program-
ming 073H into the uppermost byte the EEPROM is protect-
ed from future adaptation except for configuration data
which can always be modified
If the EEPR bit of the Signature Register is low the
EEPROM program mode may be entered The EEPR bit is
low if the EEPROM code is not programmed as 73H In this
mode if the EELOAD bit of Configuration Register B is set
the user can directly control the EEPROM signals by writing
to the Data Transfer Port The user can write to the Data
Transfer Port and the value on the SD3 SD2 and SD1 pins
will be driven onto the EECS SK and DI outputs These
outputs will be latched The user can generate a clock on
SK by repetitively writing 1 then 0 to the appropriate bit This
can be used to generate the EEPROM signals as per the
NM93C06 data sheet
When the EEPROM has been programmed the user must
give the DP83907 a reset signal to return to normal opera-
tion and to read in the new data
Storing and Loading Configuration from EEPROM
If the EECONFIG function on MSA10 is high during boot up
the DP83907’s configuration is read from the EEPROM be-
fore the PROM data is read The configuration data is stored
within the upper two words of the EEPROM’s address
space Configuration Registers A and B are located in the
lower of these words Register C in the lower byte of the
upper word as shown in Figure 7
To write this configuration into the EEPROM the user must
follow the routine specified in the pseudo code below If the
EEPROM code byte in the EEPROM is programmed as 73H
the Configuration Registers may be written to in the
EPROM This operation will work regardless of the level on
EECONFIG The EELOAD bit of Configuration Register B
being set starts the EEPROM write process Care should be
taken not to accidentally set the GDLlNK bit and therefore
disable link integrity checking The next 3 writes to this reg-
ister load the values that will be stored in the configuration
register (note that the last 2 of these writes do not have to
follow the normal practice of preceding a write to this regis-
ter with a read to this address) The DP83907 will then com-
mence the EEPROM write The write has been completed
when the EELOAD bit goes to zero This loading proce-
The