DP83907VF National Semiconductor, DP83907VF Datasheet - Page 14

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

4 0 Functional Description
ing the last transmit byte During reception the CRC logic
generates a CRC field from the incoming packet This local
CRC is serially compared to the incoming CRC appended to
the end of the packet by the transmitting node If the local
and received CRC match a specific pattern will be generat-
ed and decoded to indicate no data errors Transmission
errors result in different pattern and are detected resulting
in rejection of a packet
Transmit Serializer
The Transmit Serializer reads parallel data from the FIFO
and serializes it for transmission The serializer is clocked by
the transmit clock generated internally The serial data is
also shifted into the CRC generator checker At the begin-
ning of each transmission the Preamble and SFD Genera-
tor append 62 bits of 1 0 preamble and a 1 1 synch pattern
After the last data byte of the packet has been serialized the
32-bit FCS (Frame Check Sequence) field is shifted directly
out of the CRC generator In the event of a collision the
Preamble and SFD generator is used to generate a 32-bit
JAM pattern of all 1’s
Comparator-Address Recognition Logic
The address recognition logic compares the Destination Ad-
dress Field (first 6 bytes of the received packet) to the Phys-
ical address registers stored in the Address Register Array
FIGURE 12 DP8390 Core Simplified Block Diagram
(Continued)
14
If any one of the six bytes does not match the pre-pro-
grammed physical address the Protocol Control Logic re-
jects the packet All multicast destination addresses are fil-
tered using a hashing technique (See register description )
If the multicast address indexes a bit that has been set in
the filter bit array of the Multicast Address Register Array
the packet is accepted otherwise it is rejected by the Proto-
col Control Logic Each destination address is also checked
for all 1’s which is the reserved broadcast address
FIFO and Packet Data Operations
OVERVIEW
To accommodate the different rates at which data comes
from (or goes to) the network and goes to (or comes from)
the packet buffer memory the DP83907 contains a 16-byte
FIFO for buffering data between the media and the buffer
RAM located on the memory support bus The FIFO thresh-
old is programmable When the FIFO has filled to its pro-
grammed threshold the local DMA channel transfers these
bytes (or words) into local memory (via the memory bus) It
is crucial that the local DMA is given access to the bus
within a minimum bus latency time otherwise a FIFO under-
run (or overrun) occurs
TL F 12082 – 7