DP83950BVQB National Semiconductor, DP83950BVQB Datasheet

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... Cascadable for large hub applications Y Compatible with AUI compliant transceivers Y On-chip Elasticity Buffer Manchester encoder and de- Y coder 1 0 System Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation RIC TM and SONIC TM are trademarks of National Semiconductor Corporation C 1995 National Semiconductor Corporation TL F 11096 ...

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Connection Diagram 160 Pin PQFP Package Pin Table ( Ports Pin Name Pin No Pin Name TXO12P TXO12 39 RXI7 a b TXO12 38 RXI7 b a TXO12P 37 TXO7P a a RXI12 ...

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... Connection Diagram 160 Pin PQFP Package (Continued) Ports 2– Port 1 AUI Order Number DP83950BVQB See NS Package Number VUL160A 11096 – 42 ...

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Connection Diagram 160 Pin PQFP Package Pin Table (1–5 AUI Pin Name Pin No Pin Name TXO12P TXO12 39 RXI7 a b TXO12 38 RXI7 b a TXO12P 37 TXO7P a a RXI12 36 TXO7 ...

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... Connection Diagram 160 Pin PQFP Package (Continued) Ports 6– Ports 1– 5 AUI Order Number DP83950BVQB See NS Package Number VUL160A 11096 – 43 ...

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Connection Diagram 160 Pin PQFP Package Pin Table (1–7 AUI Pin Name Pin No Pin Name TXO12P TXO12 39 RX7 a a TXO12 38 RX7 b b TXO12P 37 CD7 a a RXI12 36 CD7 ...

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... Connection Diagram 160 Pin PQFP Package (Continued) Ports 8– Ports 1– 7 AUI Order Number DP83950BVQB See NS Package Number VUL160A 11096 – 44 ...

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Connection Diagram 160 Pin PQFP Package Pin Name Pin No Pin Name TX12 TX12 39 RX7 a a CD12 38 RX7 b b CD12 37 CD7 a a RX12 36 CD7 a b RX12 35 ...

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... Connection Diagram 160 Pin PQFP Package (Continued) All AUI Ports Order Number DP83950BVQB See NS Package Number VUL160A 11096 – 45 ...

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Connection Diagram 160 Pin PGA Package Pin Table ( Ports Pin Name Pin No Pin Name TXO12P A15 RXI7 b b TXO12 A14 RXI7 a a TXO12 B14 TXO7P b a TXO12P C13 TXO7 a b ...

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Connection Diagram 160 Pin PGA Package (Continued) Bottom View 1 AUI 2 – Ports a Order Number DP83950BNU See NS Package Number UP159A 11096– 2 ...

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Connection Diagram 160 Pin PGA Package Pin Table (1–5 AUI Pin Name Pin No Pin Name TXO12P A15 RXI7 b b TXO12 A14 RXI7 a a TXO12 B14 TXO7P b a TXO12P C13 TXO7 a b RXI12 B13 ...

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Connection Diagram 160 Pin PGA Package (Continued) Bottom View 1–5 AUI 6– Ports a Order Number DP83950BNU See NS Package Number UP159A 11096– 3 ...

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Connection Diagram 160 Pin PGA Package Pin Table (1–7 AUI Pin Name Pin No Pin Name TXO12P A15 RX7 b a TXO12 A14 RX7 a b TXO12 B14 CD7 b a TXO12P C13 CD7 a b RXI12 B13 ...

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Connection Diagram 160 Pin PGA Package (Continued) Bottom View 1–7 AUI 8– Ports a Order Number DP83950BNU See NS Package Number UP159A 11096– 4 ...

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Connection Diagram 160 Pin PGA Package Pin Name Pin No Pin Name TX12 A15 RX7 b a TX12 A14 RX7 a b CD12 B14 CD7 b a CD12 C13 CD7 a b RX12 B13 TX7 a a RX12 ...

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Connection Diagram 160 Pin PGA Package (Continued) Bottom View All AUI Ports Order Number DP83950BNU See NS Package Number UP159A 11096– 5 ...

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Pin Descriptions Pin Pin No Name NETWORK INTERFACE PINS (On-Chip Transceiver Mode) RXI2 to RXI13 b b RXI2 to RXI13 a a TXOP2 to TXOP13 b b TXO2 to TXO13 b b TXO2 to TXO13 a a TXOP2 ...

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Pin Descriptions (Continued) Pin Pin Driver Name Type PROCESSOR BUS PINS RA0–RA4 TT I REGISTER ADDRESS INPUTS These five pins are used to select a register to be read or written The state of these ...

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Pin Descriptions (Continued) Pin Pin Driver Name Type INTER-RIC BUS PINS ACKI TT I ACKNOWLEDGE INPUT Input to the network ports’ arbitration chain ACKO TT O ACKNOWLEDGE OUTPUT Output from the network ports’ arbitration chain ...

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Pin Descriptions (Continued) Pin Pin Driver Name Type MANAGEMENT BUS PINS MRXC MANAGEMENT RECEIVE CLOCK When asserted this signal provides a clock signal for the MRXD serial data stream The MRXD signal ...

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Block Diagram 22 ...

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Functional Description The repeater specification details a number of func- tions a repeater system must perform These requirements allied with a need for the implementation to be multiport strongly favors the choice of a ...

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... This is similar to the Inter-RIC bus since it allows the data packet to be recovered from the receiving RIC Unlike the Inter-RIC bus the intended recipient is not another RIC but National Semiconductor’s DP83932 ‘‘SONIC ’’ Network controller The use of a dedicated bus ...

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Functional Description FIGURE 5 3 IEEE Repeater Main State Diagram (Continued 11096– 8 ...

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Functional Description Port State Machine (PSM) There are two primary functions for the PSM as follows 1 Control the transmission of repeated data and jam sig- nals over the attached segment 2 Decide whether a port will be ...

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Functional Description ACTN Function This signal denotes there is activity on PORT N or PORT M Conditions A RIC must contain PORT N or PORT M required for a RIC to drive Note Although this signal normally has ...

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Functional Description The second method of PORT identification avoids this problem This second technique relies on an external parallel arbiter which monitors all of the RIC’s ACKO signals and responds to the RIC with the ...

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Functional Description Note In this example the Inter-RIC bus is configured to use active low signals (Continued) FIGURE 5 4 RIC System Topology 11096 – 9 ...

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Functional Description Note 1 The activity shown in RX represents the transmitted signal Note In this example the Inter-RIC bus is configured to use active low signals (Continued) after being looped back by the attached ...

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Functional Description Note 1 SEND PREAMBLE SEND SFD SEND DATA Note In this example the Inter-RIC bus is configured to use active low signals (Continued) FIGURE 5 6 Receive Collision 11096 – 11 ...

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Functional Description Receive Collisions A receive collision is a collision which occurs on the network segment attached to PORT the collision is ‘‘re- ceived’’ similar manner as a data packet is received and ...

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Functional Description on the network (this may be deduced since ANYXN is inac- tive) so the repeater will move to the ONE PORT LEFT state The RIC system treats this state in a similar manner to a receive ...

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Functional Description Jabber Protection A repeater is required to disable transmit activity if the length of its current transmission reaches the jabber protect limit This is defined by the specification’s Tw3 time The repeater disables output for a ...

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Functional Description Note DE Bus Drive Enable Active High RE Bus Receive Enable active low e e Note In this example the Inter-RIC bus is shown as using active low signals FIGURE 5 9 External Bus Transceiver Connection ...

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Functional Description 5 4 DESCRIPTION OF HARDWARE CONNECTION FOR INTER-RIC BUS When considering the hardware interface the Inter-RIC bus may be viewed as consisting of three groups of signals 1 Port Arbitration chain namely ACKI and ACKO 2 ...

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Functional Description TABLE 5 1 Pin Definitions for Options in the Mode Load Operation Pin Programming Effect When Name Function Bit resv Not Permitted D1 tw2 5 bits D2 CCLIM 63 D3 LPPART Selected D4 ...

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Functional Description TABLE 5 1 Pin Definitions for Options in the Mode Load Operation (Continued) Pin Programming Effect When Name Function Bit is 0 RA0 BYPAS1 RA1 BYPAS2 RA2 BINV Active High Signals RA3 EXPLL External PLL RA4 ...

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Functional Description 5 6 DESCRIPTION OF HARDWARE CONNECTION FOR PROCESSOR AND DISPLAY INTERFACE Display Update Cycles The RIC possesses control logic and interface pins which may be used to provide status information concerning activi the attached ...

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Functional Description Table 5 3 Status Display Pin Functions in MAXIMUM MODE Signal Pin Name D0 Provides status information concerning the Link Integrity status of 10BASE-T segments This signal should be connected to the data inputs of the ...

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Functional Description (Continued) 41 ...

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Functional Description FIGURE 5 13 Processor Connection Diagram (Continued 11096– 17 ...

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Functional Description Processor Access Cycles Access to the RIC’s on-chip registers is made via its proces- sor interface This utilizes conventional non-multiplexed ad- dress (five bit) and data (eight bit) busses The data bus is also used to ...

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Hub Management Support Each counter is 16 bits long and may be directly read by the processor Additionally each counter has a number of de- codes to indicate the current value of the count There are three decodes ...

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Hub Management Support Out of Window Collision (OWC) The out of window colli- sion flag for a port goes active when a collision is experi- enced outside of the network slot time Partition (PART) This flag goes active ...

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Hub Management Support providing information of six different types They are held in seven Packet Status Registers ‘‘PSRs’’ 1 The RIC and port address fields PSR(0) and (1) can uniquely identify the repeater port receiving the packet out ...

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Hub Management Support (Continued) 47 ...

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Hub Management Support Packet Status Register Bit Symbol D0 resv RESERVED FOR FUTURE USE This bit is currently undefined management software should not examine the state of ...

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Hub Management Support Packet Status Register OWC NSFD PLER ELBER Bit Symbol D(1 0) CT(9 8) COLLISION TIMER BITS 9 AND 8 These two bits are the upper bits of the collision ...

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Port Block Functions (Continued TRANSCEIVER FUNCTIONS The RIC may connect to network segments in three ways 1 Over AUI cable to transceiver boxes 2 Directly to board mounted transceivers 3 To twisted pair cable via a ...

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Port Block Functions (Continued PORT STATUS REGISTER FUNCTIONS Each RIC port has its own status register In addition to providing status concerning the port and its network seg- ment the register allows the following operations to ...

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Port Block Functions (Continued) FIGURE 7 2 Port Connection to a 10BASE2 Segment (AUI Interface Selected) The preceding diagrams show a RIC port (Numbers 2 to 13) connected to a 10BASE-T and a 10BASE2 segment The values of ...

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Port Block Functions (Continued) FIGURE 7 3 IEEE Segment Partition Algorithm 11096 – 21 ...

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RIC Registers RIC Register Address Map The RIC’s registers may be accessed by applying the re- quired address to the five Register Address (RA(4 0)) input pins Pin RA4 makes the selection between the upper and lower halves ...

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RIC Registers (Continued) Address Page (0) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H Device Type Register 12H Lower Event Count Mask Register (ECMR) 13H Upper ECMR 14H ...

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RIC Registers (Continued) Register Array Bit Map Addresses 00H to 10H Address D7 D6 (Hex) 00 BINV BYPAS2 01 to DISPT SQL 0D 0E MINMAX DPART 0F IVCTR3 IVCTR2 Register Array Bit Map Addresses 10H to 1FH Page ...

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RIC Registers (Continued) RIC Status and Configuration Register (Address 00H) The lower portion of this register contains real time information concerning the operation of the RIC The upper three bits represent the chosen configuration of the transceiver interface ...

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RIC Registers (Continued) Port Real Time Status Registers (Address 01H to 0DH DISPT EGP PTYPE1 PTYPE0 Bit R W Symbol GDLNK GOOD LINK 0 Link pulses are being received by the ...

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RIC Registers (Continued) RIC Configuration Register (Address 0EH) This register displays the state of a number of RIC configuration bits loaded during the Mode Load operation MINMAX DPART TX ONLY OWCE Bit R W ...

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RIC Registers (Continued) Real Time Interrupt Register (Address 0FH) The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis Any remaining interrupts which have not been serviced before the following packet ...

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... FULL COUNTER This indicates one of the port event counters has a value equal to FFFF Hex Device Type Register (Page 0H Address 11H) This register may be used to distinguish different revisions of RIC If this register is read it will return a different value each for DP83950 revisions (Contact National Semiconductor for revision information ) Write operations to this register have no effect upon the contents D7 ...

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RIC Registers (Continued) Lower Event Count Mask Register (Page 0H Address 12H BDLNKC PARTC RECC SEC NSFDC Bit R W Symbol JABC JABBER COUNT ENABLE Enables recording of Jabber Protect events ...

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RIC Registers (Continued) Event Record Mask Register (Page 0H Address 14H BDLNKE PARTE OWCE SEE NSFDE Bit R W Symbol JABE JABBER ENABLE Enables recording of Jabber Protect events D1 R ...

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RIC Registers (Continued) Interrupt and Management Configuration Register (Page 0H Address 16H) This register powers up with all bits set to one and must be initialized by a processor write cycle before any events will generate interrupts D7 ...

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RIC Registers (Continued) RIC Address Register (Page 0H Address 17H) This register may be used to differentiate between RICs in a multi-RIC repeater system The contents of this register form part of the information available through the management ...

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... AC and DC Specifications Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT DC Specifications PROCESSOR LED TWISTED PAIR PORTS INTER-RIC AND MANAGEMENT INTERFACES Symbol ...

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AC and DC Specifications DC Specifications Symbol Description PSEUDO AUI (PORTS 2–13) V Differential Output POD Voltage ( Differential Output Voltage POB Imbalance ( Undershoot Voltage ...

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AC and DC Specifications RECEIVING TIMINGS AUI PORTS Receive activity propagation start up and end delays for ports in non 10BASE-T mode Number Symbol T3a rxaackol T4a rxiackoh T5a rxaactna T6a rxiactni Note ACKI assumed high Note In ...

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AC and DC Specifications RECEIVE TIMING 10BASE-T PORTS Receive activity propagation start up and end delays for ports in 10BASE-T mode Number Symbol T3t rxaackol T4t rxiackoh T5t rxaactna T6t rxiactni Note ACKI assumed high TRANSMIT TIMING AUI ...

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AC and DC Specifications TRANSMIT TIMING 10BASE-T PORTS Receive activity propagation start up and end delays for ports in 10BASE-T mode Number Symbol T15t actnatxa Note ACKI assumed high Note ACTN and ACTN are tied together d s ...

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AC and DC Specifications COLLISION TIMING AUI PORTS Collision activity propagation start up and end delays for ports in non 10BASE-T mode RECEIVE COLLISION TIMING Number Symbol T32a cdacolna CD Active to COLN Active (Note 1) T33a cdicolni ...

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AC and DC Specifications COLLISION TIMING ALL PORTS Number Symbol T34 anyamin ANYXN Active Time T35 anyitxai ANYXN Inactive all Inactive T38 anyasj ANYXN Active to Start of Jam Number Symbol T36 actnitxi ACTN Inactive ...

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AC and DC Specifications INTER RIC BUS OUTPUT TIMING Number Symbol T101 ircoh T102 ircol T103 ircoc T104 actndapkena T105 actndairea T106 ireoairca T107 irdov T108 irdos T109 ircohirei T110 ircclks Note In these diagrams the Inter-RIC and ...

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AC and DC Specifications INTER RIC BUS INPUT TIMING Number Symbol T111 ircih T112 ircil T114 irdisirc T115 irdihirc T116 irchiire Note In these diagrams the Inter-RIC and Management Busses are shown using active high signals active low ...

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AC and DC Specifications MANAGEMENT BUS TIMING Number Symbol T50 mrxch MRXC High Time T51 mrxcl MRXC Low Time T52 mrxcd MRXC Cycle Time T53 actndamena ACTNd Active to MEN Active T54 actndamcrsa ACTNd Active to MCRS Active ...

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AC and DC Specifications MLOAD TIMING Number Symbol T61 mldats Data Setup T62 mldath Data Hold T63 mlabufa MLOAD Active to BUFEN Active T64 mlibufi MLOAD Inactive to BUFEN Inactive T65 mlw MLOAD Width STROBE TIMING Number Symbol ...

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AC and DC Specifications REGISTER READ TIMING Number Symbol T80 rdadrs Read Address Setup T81 rdadrh Read Address Hold T82 rdabufa Read Active to BUFEN Active T83 rdibufi Read Inactive to BUFEN Inactive T84 rdadatv Read Active to ...

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AC and DC Specifications REGISTER WRITE TIMING Number Symbol T90 wradrs Write Address Setup T91 wradrh Write Address Hold T92 wrabufa Write Active to BUFEN Active T93 wribufi Write Inactive to BUFEN Inactive T94 wradatv Write Active to ...

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... JEDEC Molded Plastic Quad Flat Package (VUL) Units pF pF Note In the above diagram the TX AUI side of the isolation (pulse transformer) The pulse transformer used for all testing is the Pulse Engineering PE64103 Order Number DP83950BVQB NS Package Number VUL160A 11096– 37 and TX signals are taken from the a ...

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