DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 12

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

3.0 Functional Description
3.3.3 Master Read
A Master Read operation starts with the DP83820
asserting REQN. See Figure 3-6. If GNTN is asserted
within 2 clock cycles, FRAMEN, Address, and Command
will be generated 2 clocks after REQN (Address and
FRAMEN for 1 cycle only). If GNTN is asserted 3 cycles or
later, FRAMEN, Address, and Command will be generated
on the clock following GNTN.
The device will wait for 8 cycles for the assertion of
DEVSELN. After 8 clocks without DEVSELN, the device
will issue a Master Abort by asserting FRAMEN HIGH for 1
cycle. IRDYN will be forced HIGH on the following cycle.
Both signals will become tri-state on the cycle following
their deassertion.
On the clock edge after the generation of Address and
Command, the address bus will become tri-state, and the
3.3.4 Master Write
A Master Write operation starts with the DP83820
asserting REQN. See Figure 3-7. If GNTN is asserted
within 2 clock cycles, FRAMEN, Address, and Command
will be generated 2 clocks after REQN (Address and
FRAMEN for 1 cycle only). If GNTN is asserted 3 cycles or
later, FRAMEN, Address, and Command will be generated
on the clock following GNTN.
The device will wait for 8 cycles for the assertion of
DEVSELN. After 8 clocks without DEVSELN, the device
will issue a Master Abort by asserting FRAMEN HIGH for 1
cycle. IRDYN will be forced HIGH on the following cycle.
Both signals will become tri-state on the cycle following
their deassertion.
C/BEN[3:0]
DEVSELN
FRAMEN
AD[31:0]
TRDYN
IRDYN
REQN
GNTN
PAR
CLK
(Continued)
Figure 3-6 Master Read Operation
12
Addr
C/BEN bus will contain valid byte enables. On the clock
edge after FRAMEN was asserted, IRDYN will be asserted
(and FRAMEN will be deasserted if this is to be a single
read operation). On the clock where both TRDYN and
DEVSELN are detected as asserted, data will be latched in
(and the byte enables will change if necessary). This will
continue until the cycle following the deassertion of
FRAMEN.
On the clock where the second to last read cycle occurs,
FRAMEN will be forced HIGH (it will be tri-stated 1 cycle
later). On the next clock edge that the device detects
TRDYN asserted, it will force IRDYN HIGH. It, too, will be
tri-stated 1 cycle later. This will conclude the read
operation. The DP83820 will never force a wait state during
a read operation.
On the clock edge after the generation of Address and
Command, the data bus will become valid, and the C/BEN
bus will contain valid byte enables. On the clock edge after
FRAMEN was asserted, IRDYN will be asserted (and
FRAMEN will be deasserted if this is to be a single read
operation). On the clock where both TRDYN and
DEVSELN are detected as asserted, valid data for the next
cycle will become available (and the byte enables will
change if necessary). This will continue until the cycle
following the deassertion of FRAMEN.
On the clock where the second to last write cycle occurs,
FRAMEN will be forced HIGH (it will be tri-stated 1 cycle
later). On the next clock edge that the device detects
TRDYN asserted, it will force IRDYN HIGH. It, too, will be
tri-stated 1 cycle later. This will conclude the write
operation. The DP83820 will never force a wait state during
a write operation.
Data
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