DP83820BVUW National Semiconductor, DP83820BVUW Datasheet - Page 52

• Manufacturer Part Number: DP83820BVUW
• Description: IC INTERFACE CONTROLLER 208-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83820BVUW

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: IEEE 802.3
• Voltage - Supply: 3.3V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83820BVUW

4.0 Register Set
4.2.16 Receive Configuration Register
This register is used to set the receive configuration for DP83820. Receive properties such as accepting error packets,
runt packets, setting the receive drain threshold etc. are controlled here
25-23
22-20
19-6
bit
31
30
29
28
27
26
STRIPCRC
MXDMA
RX_FD
AIRL
AEP
ARP
ALP
tag
Offset: 0038h
(Continued)
Tag: RXCFG
Accept Errored Packets
Accept Runt Packets
Strip CRC
Receive Full Duplex
Accept Long Packets
Accept In-Range Length
Errored Packets
Max DMA Burst Size per Rx
DMA Burst
description
Access: Read Write
When set to 1, all packets with CRC or alignment errors will be accepted.
When set to 0, all packets with CRC or alignment errors will be rejected if
possible. Note that depending on the type of error, some packets may be
received with errors, regardless of the setting of AEP . These errors will be
indicated in the CMDSTS field of the last descriptor in the packet.
When set to 1, all packets under 64 bytes in length without errors are
accepted. When this bit is 0, all packets less than 64 bytes in length will be
rejected if possible.
When set to a 1, the CRC will be stripped from the receive packet and the
byte count adjusted appropriately.
When set to 1, data received simultaneously to a local transmission (such
as during a PMD loopback or full duplex operation) will be accepted as valid
received data. When set to 0 (default), all data received simultaneous to a
local transmit will be rejected. This bit must be set to 1 for PMD loopback
and full duplex operation.
When set to 1, all packets > 1518 bytes in length and <= 65527 bytes will
be treated as normal receive packets, and will not be tagged as long or
error packets. All packets > 65527 bytes in length will be truncated at 65528
bytes and either rejected from the FIFO, or tagged as long packets. Care
must be taken when accepting long packets to ensure that buffers provided
are of adequate length. When ALP is set to 0, packets larger than 1518
bytes (CRC inclusive) will be truncated at 1514 bytes, and rejected if
possible.
When set to 1, packets with Length/Type fields that do not match the data
length of the packet will be accepted. When set to 0, packets with
Length/Type fields that do not match the data length of the packet will be
rejected. In-Range Length checking only occurs if the Length/Type field is a
valid length.
unused
This field sets the maximum size of receive DMA data bursts according to
the following table:
000 = 256 32-bit words (1024 bytes)
001 = 2 32-bit words (8 bytes)
010 = 4 32-bit words (16 bytes)
011 = 8 32-bit words (32 bytes)
100 = 16 32-bit words (64 bytes)
101 = 32 32-bit words (128 bytes)
110 = 64 32-bit words (256 bytes)
111 = 128 32-bit word (512 bytes)
unused
Size: 32 bits
52
usage
Hard Reset: 00000004h
Soft Reset: 00000004h
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