MC33889DW Freescale Semiconductor, MC33889DW Datasheet
MC33889DW
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... MOTOROLA Freescale Semiconductor, Inc. Semiconductor Technical Data Product Preview System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface The MC33889 is a monolithic integrated circuit combining many functions frequently used by automotive ECUs. It incorporates a low speed fault tolerant CAN physical interface. ...
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... Freescale Semiconductor, Inc. 1 MAXIMUM RATINGS Ratings ELECTRICAL RATINGS Supply Voltage at Vsup - Continuous voltage - Transient voltage (Load dump) Logic Inputs (Rx, Tx, MOSI, MISO, CSB, SCLK, Reset, WDOGB, INTB) Output current Vdd1 HS1 - voltage - output current ESD voltage (HBM 100pF, 1.5k) - CANL, CANH, Rtl, Rth, HS1, L0, L1 ...
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... Freescale Semiconductor, Inc. 2 ELECTRICAL CHARACTERISTICS (V From 5.5V to 18V and T from -40°C to 125°C) unless otherwise noted. For all pins except can related pins sup j Description Vsup pin (Device power supply) Nominal DC Voltage range Extended DC Voltage range 1 Extended DC Voltage range 2 Input Voltage during Load Dump ...
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... Freescale Semiconductor, Inc. (V From 5.5V to 18V and T from -40°C to 125°C) unless otherwise noted. For all pins except can related pins sup j Description Idd1 stop output current to wake up SBC Idd1 stop output current to wake up SBC Idd1 over current wake deglitcher (with ...
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... Freescale Semiconductor, Inc. (V From 5.5V to 18V and T from -40°C to 125°C) unless otherwise noted. For all pins except can related pins sup j Description Low Level Output Voltage (I =1.5mA) 0 High Level Output Voltage (I =-250uA) 0 INT Pin Low Level Output Voltage (I =1.5mA) 0 High Level Output Voltage (I ...
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... Freescale Semiconductor, Inc. (V From 5.5V to 18V and T from -40°C to 125°C) unless otherwise noted. For all pins except can related pins sup j Description Time from Falling or Rising Edges of CS to: - MISO Low Impedance - MISO High Impedance Time from Rising Edge of SCLK to MISO ...
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... Freescale Semiconductor, Inc. Delay between SPI and “CAN normal mode” Delay between SPI and “CAN sleep mode” Delay between CSB wake up (CSB low to high) and SBC normal request mode (Vdd1 on & reset high) Delay between CSB wake up (CSB low ...
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... Freescale Semiconductor, Inc. 3 CAN MODULE SPECIFICATION ELECTRICAL RATINGS Ratings DC Voltage On Pins Tx voltage at V2 (V2int) DC Voltage On Pins CANH, CANL Transient Voltage At Pins CANH, CANL 0 < V < 5.5V < 500ms 2-int sup Transient Voltage On Pins CANH, CANL (Coupled Through 1nF Capacitor) DC Voltage On Pins Rth, Rtl Transient Voltage At Pins RtH, RtL 0 < ...
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... Freescale Semiconductor, Inc. Conditions Differential Receiver, Dominant To Recessive Threshold (Bus Failures CANH Recessive Output Voltage TX = 5V; R < 4k (RTH) CANL Recessive Output Voltage TX =5V; R < 4k (RTL) CANH Output Voltage, Dominant -40mA; Normal Operating Mode CANH CANL Output Voltage, Dominant 40mA; Normal Operating Mode ...
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... Freescale Semiconductor, Inc. Conditions CAN Module Thermal Shutdown AC CHARACTERISTICS V From 5.5V to 18V and T ( sup CANL and CANH Slew Rates (10% to 90%). Rising or Falling Edges. Note 1.Recessive to Dominant state. CANL and CANH Slew Rates (10% to 90%). Rising or Falling Edges. Note 1.Dominant to Recessive. Note 1. Propagation Delay Low. Note 2. ...
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... Freescale Semiconductor, Inc. Tx high: RECESSIVE Bit V TX CANL CANH V diff onRX RECESSIVE Bit Figure 4. Test Circuit for AC Characteristics For More Information On This Product, PC33889 PC33889 DEVICE DESCRIPTION Figure 3. Device Signal Waveforms Tx low: DOMINANT Bit V th(rd) t DOMINANT Bit VDD R C CANL C CANH ...
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... Freescale Semiconductor, Inc. 4 DEVICE DESCRIPTION Introduction: The MC33889 is an integrated circuit dedicated to automotive applications. It includes the following functions: - One full protected voltage regulator with 200mA total output current capability. - Driver for external path transistor for V2 regulator function. - Reset, programmable watchdog function ...
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... Freescale Semiconductor, Inc. In stop mode the Software watchdog can be “running” or “not running” depending upon selection by SPI. Refer to SPI description, RCR register bit WDSTOP. If W/D is enabled the SBC must be wake up before W/D time expired, otherwise a reset is generated. In stop mode, SBC wake up capability are identical as in sleep mode. ...
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... Freescale Semiconductor, Inc. 4.9.1 Wake up from wake up inputs (L0, L1) without cyclic sense: The wake up lines are dedicated to sense external switches state and if changes occur to wake up the MCU (In sleep or stop modes). The wake up pins are able to handle 40V DC. The internal threshold is 3V typical and these inputs can be used as input port expander ...
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... Freescale Semiconductor, Inc. Vdd1 Reset WDOGB SPI W/D clear SPI CSB The Wdogb output pin is a push pull structure than can drive external component of the application in order for instance to sig- nal MCU wrong operation. Even internally turned on (low sate) the reset pins can be forced 25°C only, thanks to its internal limited current drive capability ...
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... Freescale Semiconductor, Inc. external signal sources to zero or 5V and this without damage. This allow for instance to supply the complete application board by external power supply and to apply the correct signal to reset pins. 4.17 Gnd Shift Detection 4.17.1 General When normally working in two-wire operating mode, the CAN transmission can afford some ground shift between different nodes without trouble ...
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... Freescale Semiconductor, Inc. 5 TABLE OF OPERATION The table below describe the SBC operation modes. Voltage Wake up mode Regulator capabilities HS1 switch (if enabled) Vdd1: ON Normal V2: OFF Request HS1: OFF Vdd1: ON V2: ON Normal HS1 controllable Vdd1: ON V2: OFF Standby HS1 controllable Vdd1: ON CAN (always ...
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... Freescale Semiconductor, Inc. SIMPLIFIED STATE MACHINE Reset (1ms) expired Reset Vdd1 low OR W/D: time out 350ms & !Nostop Power Down (Vdd1 high temperature OR (Vdd1 low > 100ms & Vsup >BFew)) & Nostop & !BATFAIL denotes priority State machine description: “Nostop” means Nostop bit = 1 “ ...
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... Freescale Semiconductor, Inc. Normal Request Normal Simplified State machine in debug modes Wake up Stop (1) Normal Request R R Stop debug Standby Debug (1) If stop mode entered entered without watchdog, no matter the WDSTOP bit. (E) debug mode entry point (step 5 of the debug mode entering sequence). ...
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... Freescale Semiconductor, Inc. 6 TYPICAL APPLICATIONS Vbat Vsup HS1 L0 L1 Rth Rrth CAN H CAN L Rrtl Rtl Fig 1: Simplified typical application with ballast transistor Vbat Vsup HS1 L0 L1 Rth Rrth CAN H CAN L Rrtl Rtl Fig 2: Simplified typical application without ballast transistor PC33889 PC33889 ...
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... Freescale Semiconductor, Inc. 7 SPI INTERFACE 7.1 Data format description Bit7 Bit6 Bit5 Bit4 MISO R/W address The SPI bit SPI. First 3 bits are used to identify the internal SBC register address, bit read/write bit. The last 4 bits are data send from MCU to SBC or read back from SBC to MCU. ...
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... Freescale Semiconductor, Inc. 7.2 Register description 7.2.1 MCR Register MCR W $000b R Reset Reset condition Table 7-2. Control bits MCTR2 MCTR1 MCTR0 (1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when Vsup falls below 3V. (2): Watchdog ON or OFF depends upon RCR register bit D3. ...
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... Freescale Semiconductor, Inc. 7.2.2 RCR register RCR W WDSTOP $001b R Reset Reset condition POR, RESET Table 7-3. Control bits Status bit Bit value WDSTOP NOSTOP RSTTH CANWU TXFAILURE 7.2.3 CAN register Some description. CAN W $010b R Reset Reset condition POR, CAN Table 7-4. ...
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... Freescale Semiconductor, Inc. By setting CEXT to 1 the transceiver cell supports sub bus communication. CEXT Table 7-6. FDIS 0 1 Disable (L0 wake up threshold is low level only, no matter D0 and D1 bits set in WUR register). note: if DFIS bit is set to 1, WUR register must be read before going into sleep or stop mode in order to clear the wake up flag. ...
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... Freescale Semiconductor, Inc. Control bits GSLR1 Table 7-9. gnd shift selection SHIFT 0 1 Status bits Status bit HS1OT (*) SHIFT V2LOW VSUPLOW (*) Once the HS1 switch has been turned off because of over temperature, it can be turned on again by setting the appropriate control bit to “1”. ...
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... Freescale Semiconductor, Inc. Control bits:. LCTR3 LCTR2 LCTR1 Table 7-11. Status bits: FDIS bit in L0WUb L0WUa CAN register L1WUb L1WUa 7.2.6 TIM registers Description: This register is splitted into 2 sub registers, TIM1 and TIM2. TIM1 controls the watchdog timing selection as well as the window or time out option. TIM1 is selected when bit ...
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... Freescale Semiconductor, Inc. TIM1 Reset Reset condition Table 7-12. Description WDW WDT1 Table 7-13. jWatchdog operation (window and time out) window closed for watchdog clear no watchdog clear allowed WD timing * 50% WD timing * 50% Watchdog period (WD timing selected by TIM 2 bit WDW=1) Window watchdog 7.2.8 ...
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... Freescale Semiconductor, Inc. CSP2 Table 7-15. Cyclic sense timing HS1 sample 7.2.9 LPC register Description: This register controls: - The state of HS1 in stop and sleep mode (HS1 permanently off or HS1 cyclic) - Enable or Disable the forced wake up function (SBC automatic wake up after time spend in sleep or stop mode, time defined by TIM2 register) - Enable or disable the sense of the wake up inputs (Lx) at sampling point of the cyclic sense period (LX2HS1 bit) ...
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... Freescale Semiconductor, Inc. Bit FWU IDDS 7.2.10 INTR register INTR W VSUPLOW $111b R VSUPLOW Reset Reset condition POR, RESET Table 7-18. Control bits: Control bit CANF VDDTEMP HS1OT-V2LOW VSUPLOW When the mask bit has been set, INTB pin goes low if the appropriate condition occurs. ...
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... Freescale Semiconductor, Inc PIN 1 IDENT e B 0.025 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...