MC33889DW Freescale Semiconductor, MC33889DW Datasheet - Page 15

• Manufacturer Part Number: MC33889DW
• Description: IC SYSTEM BASE W/CAN 28-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33889DW

• Controller Type: System Basis Chip
• Interface: CAN
• Voltage - Supply: 5.5 V ~ 18 V
• Current - Supply: 45mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PC33889
The Wdogb output pin is a push pull structure than can drive external component of the application in order for instance to sig-
nal MCU wrong operation. Even if it is internally turned on (low sate) the reset pins can be forced to 5V at 25°C only, thanks to
its internal limited current drive capability. Wdogb stays low until the Watchdog register is properly addressed through SPI.
4.16
SBC dedicated routine must be debugged. Following features allow the user to debug the software by allowing the possibility to
disable the SBC internal software watchdog timer.
4.16.1
every 350ms. In order to allow software debug and avoid MCU reset the Reset pin can be connected directly to Vdd1 by a jumper.
4.16.2
disabling the watchdog during SBC normal operation the watchdog disable has to be done with the following sequence:
hardware debug.
4.16.3
the following capabilities: The Vdd1 can be forced by an external power supply to 5V and the reset and Wdogb outputs by
When the SBC is mounted on the same printed circuit board as the micro controller it supplies, both application software and
At SBC power up, the Vdd1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
The software watchdog can be disabled through SPI. In order to avoid unwanted watchdog disable and to limit the risk of
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode)
Step 3) Write to TIM1 register to allow SBC to enter Normal mode
Step 4) Write to MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000)
Step 5) Write to MCR register normal debug (0001 x101), standby debug (0001 x110) or Stop debug (0001 x111)
While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and
Step 6) To leave the debug mode, write 0000 to MCR register.
To avoid entering debug mode after a power up, first read BATFAIL bit (MCR read) and write 0000 into MCR.
The graph below illustrates the debug mode entering.
In order to allow the possibility to download software into the application memory (MCU EEPROM or Flash) the SBC allows
debug mode
Batfail
Debug mode Application hardware and software debug with the SBC.
Device power up, reset pin connected to Vdd1
Debug modes with software watchdog disabled though SPI (Normal Debug, Standby Debug and Stop Debug)
Vdd1
MCU flash programming configuration
VSup
SPI
TIM1(step 3)
W/D clear
SPI CSB
WDOGB
SPI
Reset
Vdd1
MCR(step4)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5. Reset and Wdogb function diagram
MCR (step5)
Figure 6. Debug mode enter
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Watchdog
period
Watchdog register addressed
SPI: read batfail
SBC in debug Mode, no W/D
PC33889
Watchdog time out
MCR (step6)
SBC not in debug Mode and W/D on
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