KSZ8721B Micrel Inc, KSZ8721B Datasheet - Page 6

• Manufacturer Part Number: KSZ8721B
• Description: IC TXRX PHY 10/100 2.5V 48-SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721B

• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Data Rate: 100Mbps
• Supply Voltage Range: 2.375V To 2.625V
• Logic Case Style: SSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 2 - 1 Year
• Ic Function: Transceiver IC
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1627 - BOARD EVALUATION FOR KSZ8721BMC576-1626 - BOARD EVALUATION FOR KSZ8721BL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1026-5; 576-1510-5; 576-1510-5; KSZ8721B

Pin Description
Note 1.
M9999-030106
Pin Number
Pin Number
Pin Number
10
10
10
10
10
12
12
12
12
12
13
13
13
13
13
14
14
14
14
14
15
15
15
15
15
16
16
16
16
16
17
17
17
17
17
18
18
18
18
18
19
19
19
19
19
20
20
20
20
20
21
21
21
21
21
24
24
24
24
24
11
11
11
11
11
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
8
8
8
8
9
9
9
9
9
Pwr = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Gnd = ground
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
NC = No connect
PCS_LPBK
PCS_LPBK
PCS_LPBK
PCS_LPBK
PCS_LPBK
RXER/ISO
RXER/ISO
RXER/ISO
RXER/ISO
RXER/ISO
Pin Name
Pin Name
Pin Name
COL/RMII
COL/RMII
COL/RMII
COL/RMII
COL/RMII
PHYAD1
PHYAD1
PHYAD1
PHYAD1
PHYAD1
PHYAD2
PHYAD2
PHYAD2
PHYAD2
PHYAD2
PHYAD3
PHYAD3
PHYAD3
PHYAD3
PHYAD3
PHYAD4
PHYAD4
PHYAD4
PHYAD4
PHYAD4
REFCLK
REFCLK
REFCLK
CRSDV/
CRSDV/
CRSDV/
CRSDV/
CRSDV/
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
RXDV/
RXDV/
RXDV/
RXDV/
RXDV/
RXD3/
RXD3/
RXD3/
RXD3/
RXD3/
RXD2/
RXD2/
RXD2/
RXD2/
RXD2/
RXD1/
RXD1/
RXD1/
RXD1/
RXD1/
RXD0/
RXD0/
RXD0/
RXD0/
RXD0/
VDDC
VDDC
VDDC
VDDC
VDDC
MDIO
MDIO
MDIO
MDIO
MDIO
TXER
TXER
TXER
TXER
TXER
TXEN
TXEN
TXEN
TXEN
TXEN
TXD0
TXD0
TXD0
TXD0
TXD0
TXD1
TXD1
TXD1
TXD1
TXD1
TXD2
TXD2
TXD2
TXD2
TXD2
TXD3
TXD3
TXD3
TXD3
TXD3
MDC
MDC
MDC
MDC
MDC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TXC/
TXC/
TXC/
TXC/
TXC/
RXC
RXC
RXC
RXC
RXC
Type
Type
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Pwr
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
I/O
I/O
I/O
I/O
(Note 1)
(Note 1)
O
O
O
O
O
I
I
I
I
I
Pin Function
Pin Function
Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up
Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up
Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up
Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up
Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up
resistor.
resistor.
resistor.
resistor.
resistor.
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
data interface
data interface
data interface
data interface
data interface
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
latched as PHYADDR [1] during reset. See “Strapping Options” section for
latched as PHYADDR [1] during reset. See
latched as PHYADDR [1] during reset. See
latched as PHYADDR [1] during reset. See
latched as PHYADDR [1] during reset. See
details.
details.
details.
details.
details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
during reset. See “Strapping Options” section for details.
during reset. See
during reset. See
during reset. See
during reset. See
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
during reset. See “Strapping Options” section for details.
during reset. See
during reset. See
during reset. See
during reset. See
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
during reset. See “Strapping Options” section for details.
during reset. See
during reset. See
during reset. See
during reset. See
Digital IO 2.5 /3.3V tolerance power supply.
Digital IO 2.5 /3.3V tolerance power supply.
Digital IO 2.5 /3.3V tolerance power supply.
Digital IO 2.5 /3.3V tolerance power supply.
Digital IO 2.5 /3.3V tolerance power supply.
Ground.
Ground.
Ground.
Ground.
Ground.
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
pcs_lpbk during reset. See “Strapping Options” section for details.
pcs_lpbk during reset. See
pcs_lpbk during reset. See
pcs_lpbk during reset. See
pcs_lpbk during reset. See
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
during reset. See “Strapping Options” section for details.
during reset. See
during reset. See
during reset. See
during reset. See
Ground.
Ground.
Ground.
Ground.
Ground.
Digital core 2.5V only power supply.
Digital core 2.5V only power supply.
Digital core 2.5V only power supply.
Digital core 2.5V only power supply.
Digital core 2.5V only power supply.
MII Transmit Error Input.
MII Transmit Error Input.
MII Transmit Error Input.
MII Transmit Error Input.
MII Transmit Error Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Enable Input
MII Transmit Enable Input
MII Transmit Enable Input
MII Transmit Enable Input
MII Transmit Enable Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
during reset. See “Strapping Options” section for details.
during reset. See
during reset. See
during reset. See
during reset. See
Digital IO 2.5/3.3V tolerance power supply.
Digital IO 2.5/3.3V tolerance power supply.
Digital IO 2.5/3.3V tolerance power supply.
Digital IO 2.5/3.3V tolerance power supply.
Digital IO 2.5/3.3V tolerance power supply.
6
“Strapping Options” section for details.
“Strapping Options”
“Strapping Options” section for details.
“Strapping Options”
“Strapping Options” section for details.
“Strapping Options”
“Strapping Options” section for details.
“Strapping Options”
“Strapping Options” section for details.
“Strapping Options”
“Strapping Options” section for details.
“Strapping Options”
“Strapping Options” section for
“Strapping Options”
March 2006