CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 34

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

Figure 13-16.
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
■
Note: t
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■
■
Document #: 38-08013 Rev. *J
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
At = 1, SLOE is asserted. SLOE is an output enable only, whose
sole function is to drive the data bus. The data that is driven on
the bus is the data that the internal FIFO pointer is currently
pointing to. In this example it is the first data value in the FIFO.
Note: the data is pre-fetched and is driven on the bus when
SLOE is asserted.
At t = 2, SLRD is asserted. SLRD must meet the setup time of
t
the IFCLK) and maintain a minimum hold time of t
from the IFCLK edge to the deassertion of the SLRD signal).
SRD
PKTEND
FIFOADR
FLAGS
DATA
IFCLK
SLWR
SLCS
SFA
(time from asserting the SLRD signal to the rising edge of
has a minimum of 25 ns. This means when IFCLK is
shows the timing relationship of the SLAVE FIFO
t=0
Figure 13-18. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
SFA
t=1
t=2
t
t
SFD
SWR
t
N
IFCLK
t=3
t
FDH
t
WRH
t
XFLG
t
FAH
RDH
(time
T=0
t
SFA
■
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5. Note: For
the burst mode, the SLRD and SLOE are left asserted during the
entire duration of the read. In the burst read mode, when SLOE
is asserted, data indexed by the FIFO pointer is on the data bus.
During the first read cycle, on the rising edge of the clock the
FIFO pointer is updated and increments to point to address N+1.
For each subsequent rising edge of IFCLK, while the SLRD is
asserted, the FIFO pointer is incremented and the next data
value is placed on the data bus.
If the SLCS signal is used, it must be asserted with SLRD, or
before SLRD is asserted (that is, the SLCS and SLRD signals
must both be asserted to start a valid read condition).
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
IFCLK) the new data value is present. N is the first data value
read from the FIFO. In order to have data on the FIFO data
bus, SLOE MUST also be asserted.
T=1
T=2
>= t
t
SFD
SWR
N+1
t
FDH
T=3
t
SFD
N+2
XFD
t
FDH
T=4
(measured from the rising edge of
t
SFD
t
N+3
SPE
[13]
>= t
t
t
XFLG
FDH
T=5
t
WRH
PEH
CY7C68001
t
FAH
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