CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 40

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

15. General PCB Layout Guidelines
The following recommendations should be followed to ensure
reliable high-performance operation.
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Figure 16-2. Plot of the Solder Mask (White Area)
Document #: 38-08013 Rev. *J
Note
16. Source for recommendations: High Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
At least a four-layer impedance controlled boards are required
to maintain signal quality.
Specify impedance targets (ask your board vendor what they
can achieve).
To control impedance, maintain trace widths and trace spacing.
Minimize stubs to minimize reflected signals.
Connections between the USB connector shell and signal
ground must be done near the USB connector.
Bypass/flyback caps on VBus, near connector, are recom-
mended.
DPLUS and DMINUS trace lengths should be kept to within 2
mm of each other in length, with preferred length of 20–30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
It is preferred to have no vias placed on the DPLUS or DMINUS
trace routing.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
Via hole for thermally connecting the
QFN to the circuit board ground plane.
Figure 16-1. Cross section of the Area Underneath the QFN Package
PCB Material
Cu Fill
[16]
Solder Mask
0.013” dia
0.017” dia
16. Quad Flat Package No Leads (QFN)
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill is to be designed into
the PCB as a thermal pad under the package. Heat is transferred
from the SX2 through the device’s metal paddle on the bottom
side of the package. Heat from here, is conducted to the PCB at
the thermal pad. It is then conducted from the thermal pad to the
PCB inner ground plane by a 5 x 5 array of via. A via is a plated
through hole in the PCB with a finished diameter of 13 mil. The
QFN’s metal die paddle must be soldered to the PCB’s thermal
pad. Solder mask is placed on the board top side over each via
to resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
For further information on this package design please refer to
“Application Notes for Surface Mount Assembly of Amkor’s
MicroLeadFrame® (MLF®) Packages.” This application note
can be downloaded from Amkor’s web site from the following
URL:
pNote.pdf. The application note provides detailed information on
board mounting guidelines, soldering flow, rework process, etc.
Figure 16-1.
neath the package. The cross section is of only one via. The
solder paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean” type 3 solder
paste is used for mounting the part. Nitrogen purge is recom-
mended during reflow.
Figure 16-2.
displays an X-Ray image of the assembly (darker areas indicate
solder).
Figure 16-3. X-Ray Image of the Assembly
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and the Ground Plane.
Package Design Notes
Cu Fill
PCB Material
http://www.amkor.com/products/notes_papers/MLFAp-
is a plot of the solder mask pattern and
on page 40 displays a cross-sectional area under-
CY7C68001
Page 40 of 45
Figure 16-3.
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