PIC18F452-I/P Microchip Technology Inc., PIC18F452-I/P Datasheet - Page 66

• Manufacturer Part Number: PIC18F452-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/P

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
TABLE 5-2:
DS39631A-page 64
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
Legend:
Note
File Name
1:
2:
3:
4:
5:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Top-of-Stack, High Byte (TOS<15:8>)
Top-of-Stack, Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC, Low Byte (PC<7:0>)
Program Memory Table Pointer, High Byte (TBLPTR<15:8>)
Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register, High Byte
Product Register, Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
Indirect Data Memory Address Pointer 0, Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
Indirect Data Memory Address Pointer 1, Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
Indirect Data Memory Address Pointer 2, Low Byte
GIE/GIEH
STKFUL
INT2IP
RBPU
Bit 7
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520)
PEIE/GIEL
INTEDG0
STKUNF
INT1IP
Bit 6
—
—
—
—
—
—
—
—
INTEDG1
TMR0IE
bit 21
Bit 5
—
—
—
—
—
—
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT0IE
INT2IE
Bit 4
SP4
—
—
—
—
N
Preliminary
Indirect Data Memory Address Pointer 0, High Byte
Indirect Data Memory Address Pointer 1, High Byte
Bank Select Register
Indirect Data Memory Address Pointer 2, High Byte
INT1IE
RBIE
Bit 3
SP3
OV
—
TMR0IP
TMR0IF
Bit 2
SP2
—
Z
‘
0
’
. Reset values are shown for 40/44-pin devices;
INT0IF
INT2IF
Bit 1
SP1
DC
—
 2004 Microchip Technology Inc.
INT1IF
RBIP
Bit 0
RBIF
SP0
‘
0
C
’
. See Section 2.6.4 “PLL in
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
---- 0000
xxxx xxxx
xxxx xxxx
---- 0000
xxxx xxxx
---- 0000
---- 0000
xxxx xxxx
---x xxxx
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
‘
0
’
. This bit is
on page:
Details
49, 54
49, 54
49, 54
49, 55
49, 54
49, 54
49, 54
49, 76
49, 76
49, 76
49, 76
49, 89
49, 89
49, 93
49, 94
49, 95
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
49, 69
50, 69
50, 69
50, 59
50, 69
50, 69
50, 69
50, 69
50, 69
50, 69
50, 69
50, 67
49