PIC18F452-I/P Microchip Technology Inc., PIC18F452-I/P Datasheet - Page 68

• Manufacturer Part Number: PIC18F452-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/P

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
TABLE 5-2:
DS39631A-page 66
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
TRISA7
PSPIP
PSPIF
PSPIE
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
EEPGD
CSRC
RA7
SPEN
Bit 7
RD7
RC7
RB7
IBF
—
—
(5)
REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) (CONTINUED)
(2)
(2)
(2)
(5)
(5)
TRISA6
PLLEN
LATA6
RA6
CFGS
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
RX9
OBF
RD6
RC6
RB6
TX9
—
—
(5)
(5)
(3)
(5)
Data Direction Control Register for PORTA
PORTA Data Latch Register (Read and Write to Data Latch)
SREN
TXEN
RCIP
RCIE
IBOV
RCIF
Bit 5
RD5
RC5
RB5
RA5
—
—
—
—
—
—
—
PSPMODE
SYNC
CREN
FREE
TUN4
Bit 4
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
RD4
RC4
RB4
RA4
—
—
Preliminary
WRERR
ADDEN
SENDB
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
RE3
TUN3
Bit 3
RD3
RC3
RB3
RA3
—
—
(4)
PORTE Data Latch Register
(Read and Write to Data Latch)
CCP1IP
CCP1IE
HLVDIP
HLVDIF
HLVDIE
CCP1IF
TRISE2
WREN
RE2
BRGH
FERR
TUN2
Bit 2
RD2
RC2
RB2
RA2
(2)
‘
0
’
. Reset values are shown for 40/44-pin devices;
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISE1
OERR
RE1
TRMT
TUN1
Bit 1
RD1
RC1
RB1
RA1
WR
(2)
 2004 Microchip Technology Inc.
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TRISE0
RE0
RX9D
TX9D
TUN0
Bit 0
RD0
RC0
RB0
RA0
‘
RD
0
’
. See Section 2.6.4 “PLL in
(2)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000 51, 74, 83
0000 0000 51, 74, 83
0000 0000 51, 74, 83
xx-0 x000 51, 75, 84
11-1 1111
00-0 0000
00-0 0000
1111 1111
0000 0000
0000 0000
0q-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
POR, BOR
Value on
‘
0
’
. This bit is
on page:
51, 206
51, 206
51, 213
51, 202
51, 203
52, 101
52, 100
52, 108
52, 105
52, 108
52, 105
52, 108
52, 105
Details
51, 211
52, 118
52, 114
52, 111
52, 117
52, 114
52, 111
52, 117
52, 114
52, 111
52, 97
52, 99
52, 96
52, 98
27, 52