PIC16C74B-20I/L Microchip Technology Inc., PIC16C74B-20I/L Datasheet - Page 18

• Manufacturer Part Number: PIC16C74B-20I/L
• Description: 44 PIN, 7 KB OTP, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C74B-20I/L

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16C63A/65B/73B/74B
TABLE 4-1:
DS30605C-page 18
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
Bank 1
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
Shaded locations are unimplemented, read as ‘0’.
registers clear.
(4)
Name
(4)
(4)
—
—
—
—
—
—
—
—
—
—
—
(5)
(5)
(4)
(4)
(1,4)
(6)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction register
PORTC Data Direction register
PORTD Data Direction register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
PSPIE
RBPU
CSRC
IRP
Bit 7
GIE
IBF
—
—
—
—
—
—
(2)
(5)
INTEDG
ADIE
RP1
PEIE
Bit 6
OBF
TX9
—
—
—
—
—
—
(2)
(6)
PORTA Data Direction Register
TXEN
T0CS
IBOV
RCIE
Bit 5
T0IE
2
RP0
D/A
—
—
—
C mode) Address register
—
PSPMODE
Write Buffer for the upper 5 bits of the Program Counter
SYNC
T0SE
INTE
Bit 4
TXIE
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
—
—
—
S
PORTE Data Direction bits
CCP1IE
PCFG2
BRGH
Bit 2
PS2
T0IF
R/W
—
—
Z
TMR2IE
PCFG1
TRMT
INTF
Bit 1
POR
PS1
DC
UA
—
TMR1IE
CCP2IE
PCFG0
2000 Microchip Technology Inc.
TX9D
Bit 0
RBIF
BOR
PS0
BF
C
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
0000 -010 0000 -010
0000 0000 0000 0000
---- -000 ---- -000
POR, BOR
Value on:
—
—
—
—
—
—
—
—
—
—
—
RESETS
Value on
all other
—
—
—
—
—
—
—
—
—
—
—
(3)