PIC16C74B-20I/L Microchip Technology Inc., PIC16C74B-20I/L Datasheet - Page 23
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PIC16C74B-20I/L
Manufacturer Part Number
PIC16C74B-20I/L
Description
44 PIN, 7 KB OTP, 192 RAM, 33 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16C74B-20IL.pdf
(184 pages)
Specifications of PIC16C74B-20I/L
A/d Inputs
8-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
33
Interface
I2C/SPI/USART
Memory Type
OTP
Number Of Bits
8
Package Type
44-pin PLCC
Programmable Memory
7K Bytes
Ram Size
192 Bytes
Speed
4 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number:
PIC16C74B-20I/L
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10 000
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4.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 4-5:
2000 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1 REGISTER (ADDRESS 0Ch)
PSPIF
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (clear by reading RCREG)
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (clear by writing to TXREG)
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented. This bit loca-
bit 7
Legend:
R = Readable bit
-n = Value at POR
PSPIF
R/W-0
(2)
2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is
(1)
(1)
: A/D Converter Interrupt Flag bit
: Parallel Slave Port Read/Write Interrupt Flag bit
tion is reserved on these devices.
reserved on these devices.
ADIF
R/W-0
(2)
RCIF
R-0
W = Writable bit
’1’ = Bit is set
PIC16C63A/65B/73B/74B
TXIF
R-0
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt
SSPIF
R/W-0
.
CCP1IF
R/W-0
x = Bit is unknown
TMR2IF
R/W-0
DS30605C-page 23
TMR1IF
R/W-0
bit 0
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