PIC16F877-04/P Microchip Technology Inc., PIC16F877-04/P Datasheet - Page 72
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PIC16F877-04/P
Manufacturer Part Number
PIC16F877-04/P
Description
40 PIN, 7 KB FLASH, 368 RAM, 33 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F877-04P.pdf
(218 pages)
Specifications of PIC16F877-04/P
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F87X
9.1.1
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
FIGURE 9-2:
DS30292C-page 70
SCK (CKP = 0,
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
SDI (SMP = 0)
SDI (SMP = 1)
SSPIF
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
MASTER MODE
SPI MODE TIMING, MASTER MODE
bit7
bit7
bit7
bit6
bit5
bit4
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit3
CY
)
bit2
CY
CY
)
)
2001 Microchip Technology Inc.
bit1
bit0
bit0
bit0