PIC18F4620-I/PT Microchip Technology Inc., PIC18F4620-I/PT Datasheet - Page 245

• Manufacturer Part Number: PIC18F4620-I/PT
• Description: 44 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

22.0
PIC18F2525/2620/4525/4620
High/Low-Voltage Detect module (HLVD). This is a
programmable circuit that allows the user to specify
both a device voltage trip point and the direction of
change from that point. If the device experiences an
excursion past the trip point in that direction, an inter-
rupt flag is set. If the interrupt is enabled, the program
execution will branch to the interrupt vector address
and the software can then respond to the interrupt.
REGISTER 22-1:
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the
circuitry requires some time to stabilize. The IRVST bit
is a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
 2004 Microchip Technology Inc.
HIGH/LOW-VOLTAGE DETECT
(HLVD)
bit 7
bit 6
bit 5
bit 4
bit 3-0
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
bit 7
VDIRMAG: Voltage Direction Magnitude Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
Unimplemented: Read as ‘0’
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified
HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled
HLVDL3:HLVDL0: Voltage Detection Limit bits
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Maximum setting
.
.
.
0000 = Minimum setting
VDIRMAG
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Note:
range
voltage range and the HLVD interrupt should not be enabled
devices
See Table 26-4 in Section 26.0 “Electrical Characteristics” for the specifications.
U-0
—
PIC18F2525/2620/4525/4620
have
IRVST
R-0
W = Writable bit
‘1’ = Bit is set
a
HLVDEN
R/W-0
The
(Register 22-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which
minimizes the current consumption for the device.
The block diagram for the HLVD module is shown in
Figure 22-1.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in V
point. When the bit is set, the module monitors for rises
in V
DD
High/Low-Voltage
above the set point.
HLVDL3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HLVDL2
R/W-1
DD
below a predetermined set
Detect
x = Bit is unknown
HLVDL1
R/W-0
DS39626B-page 243
Control
HLVDL0
R/W-1
register
bit 0